Part of the  

Chip Design Magazine


About  |  Contact

Archive for March, 2013

Moore’s Cycle, Fifth Horseman, Mixed Signals, and IP Stress

Friday, March 22nd, 2013

What do all of these things have in common? They were key topics addressed by Cadence, Samsung, and others at CDNLive 2013.

What does Cadence see as the future trends and challenges facing the semiconductor, EDA, and IP industries? To answer this question, I attended CDNLive2013, the company’s event for users, developers, and customers. Here are the highlights from that trip:

1. System to Silicon Verification – How It All Fits Together by Frank Schirrmeister, Group Director for Product Marketing of the System Development Suite at Cadence and blogger on the System Level Design community:

By 2015, the majority of system-on-a-chip (SoC) designs will be implemented at geometries below 90 nm. There will be fewer design starts, but each will have over 110 IP blocks with more than 70% reuse. Software will continue to dominate design activity, taking over 60% of the work effort. Software will be distributed over the entire SoC. Low power will remain a driving design constraint. SoCs will contain an ever-increasing amount of analog/mixed-signal (AMS) circuitry.

Schirrmeister discussed the challenges of sensor networks used to monitor the health of cows (bovine) in the field as but one example of the variety of mixed-signal applications. This particular design was based on the ARM Cortex MO microcontroller.

Schirrmeister noted that EDA companies have had to expand their coverage into the larger system market, thanks to changes in the semiconductor supply chain. Around 2000, the industry was very fragmented (i.e., mobile chip and IP vendors worked with handset makers, who then partnered with operating-system suppliers and finally network operators). The next 12 years resulted in various combinations of subsystem integration – the result being that EDA and IP companies like Cadence must provide software (drivers and firmware for now) to their customers. In other words, the definition of the EDA-IP “system” continues to evolve.

2. Interview about mixed-signal technology trends with Mladen Nizic, Engineering Director for Mixed Signal Solutions, and Dave DeMaria, Ecosystem Alliances, Worldwide Field Operations:

Cadence’s Mladen Nizic (background right) and Dave DeMaria (background left) talk about mixed-signal technology with John Blyler, Editor of Chip Design magazine. (Photo courtesy of Lani Wong)

The growth of the mobile market – including wireless, networking, storage, and computing – requires integrated analog/mixed-signal (AMS) and/or RF functionality combined with the digital circuit. One example of this combination is a digitally assisted, mixed-signal device (e.g., a VCO with digital calibration).

Verification of the growing analog/mixed-signal portion of SoCs is leading to better behavioral models, which abstract the analog upward to the register transfer level (RTL). This improvement provides a more consistent handoff between the analog and digital boundaries. Another improvement is the use of real number models (RNMs), which enable the discrete time transformations needed for pure digital solver simulation of analog/mixed-signal verification. This approach enables faster simulation speeds for event-driven real-time models – a benefit over behavioral models like Verilog-A.

AMS simulations are also using assertion techniques to improve verification – especially in interface testing.

One important trend is the use of statistical analysis to handle both the analog nature of mixed signals and the increasing number of operational modes. I’ll post my detailed interview with Nizic and DeMaria in an upcoming blog.

3. Keynote presentations

Lip-Bu Tan, President and CEO of Cadence, began his keynote by showcasing many of today’s most popular consumer electronics – from Google glasses and other wearable embedded electronics to Samsung gesture recognition TVs and the latest automotive infotainment systems. All of these products were made possible by the semiconductor industry.

Lip-Bu Tan, President and CEO of Cadence, addresses a full audience at the company’s CDNLive2013 event.

The consumer-electronics industry has grown, thanks to the popularity of mobile and social-media applications. These applications represent important aspects of the Internet of Things – all of those unique objects that make up the front and back end of the Internet. With over one billion users on Facebook, Tan noted that the back-end cloud computing and big-data aspects of the Internet are as critical as the front-end devices. “The semiconductor industry figures prominently in all of this,” he summarized.

Chip designers and manufacturers have had to overcome significant challenges to bring these amazing devices and infrastructure to market. But even more difficult challenges lie ahead. Tan listed several of the more critical ones – from lithography and design-rule complexity to IP integration, the proliferation of mixed-signal circuits needed to support the Internet of Things, and low-power and signal-integrity issues.

Cadences success in overcoming these challenges was due to collaboration with its partners, said Tan. For example, Cadence, ARM, and TSMC continue to collaborate on 20-nm FinFET designs. Stacked-die 3D IC technology represented another area of partnership (in this case, with TSMC’s Chip-on-Wafer-on-Substrate [CoWoS] integration process). As a final example, Tan highlighted Cadence’s 14-nm FinFET collaboration with Samsung.

On the business side of the market, Cadence has acquired several IP-rich companies over the last few years. Two recently named acquisitions – Cosmic Circuits and Tensilica – will enhance the company’s position in the mixed-signal and dataplane processing markets, respectively. (Cadence To Buy Tensilica)

In conclusion, Tan highlighted one consumer success based in part on the use of Cadence’s EDA tools and methodologies – namely, the Hero GoPro camera. Over 2.3 million units were shipped last year. He hoped that such commercial successes would help to ignite interest in the EDA industry, inspiring high-school and college students to view chip design with the same “coolness” factor as the other technology giants (e.g., Facebook and Google).

The next speaker was Samsung Electronic’s CEO, Young Sohn. He provided a customer view of the semiconductor market. Samsung’s goal is to be seen as a part of the global consumer community. One measure of the success of Samsung’s branding campaign was the company’s placement among the top 10 traditional consumer brands, replacing traditional products like software drinks.

Samsung Electronic’s CEO Young Sohn speaks at Cadence’s CDNLive2013.

Today’s post-PC era is dominated by non-Windows operating systems like Apple’s iOS and Google’s Android, said Sohn. This is one indicator of the popularity of mobile devices. Not surprisingly, most of the growth at Samsung has occurred in the mobile and cloud markets. If those market segments were removed, growth in the global semiconductor market would have been flat.

Mobile is big and getting bigger. Sohn said that the company’s vision was to create products that would share data and applications among all devices – from smartphones to smart sensors. To show that mobile is much bigger than just web access, he shared a video clip where wireless nanobots were used to kill cancer cells.

Sohn was cautious about the traditional cost and form-factor reduction enabled by the semiconductor market. “Moore’s Law is an observation. In the future, cycle times (of Moore’s Law) may increase,” he speculated.

What technologies would smartphones utilize seven years from now? A good bet would be fifth-generation (5G) cellular, low-power WiFi-based dust networks with environmental sensing and high-definition, flexible organic LED displays – all running at 13 Wh. Today’s smartphones run on 8 Wh of power or less. Sohn conceded that many innovations will be needed to achieve these features – especially in low-power design and improved energy storage (i.e., battery technology).

Sohn echoed Tan’s litany of challenges facing chip designers and manufacturers – from continued device scaling to double and triple patterning and EUV lithography obstacles for the lowest nodes. He observed that there is always a cost-versus-risk tradeoff with new technologies.

One alternative to leading-edge, lowest-node technology is 3D stacked-die ICs. For now, 3D chip packaging is as expensive as the design of the SoC. But compressing form factors in mobile is important, as with system-in-package (SiP) technologies. Sohn issued the common desire that EDA tools need to do a better job with 3D stacking designs. 3D SoC designs are like housing urbanization, said Sohn. Chips need to be denser, but also must handle the increased traffic load. This is another area where innovation is required to find a solution.

Designing chips of ever-increasing complexity is not an easy task. Neither is making those chips. Manufacturing SoCs at leading-edge foundries has become a very exclusive club. The few winners that have the money and resources to create these fabs will take the biggest share of the revenue. This creates a very high barrier for startup innovation. Sohn recommended that chip designers focus on what they do best. This approach is why the development of outside, non-internal IP is a growth segment. The challenges of manufacturing and design force IP, EDA, and foundries to work together to build successful products.

Innovations are needed to overcome future design and manufacturing issues. This innovation will probably lead to disruptive technologies. To encourage this innovation, the company recently launched the Samsung Strategy and Innovation Center (SSIC), which will invest $1.1 billion in existing and disruptive technologies. Such an investment will help the company maintain its position as the so-called “fifth horseman” alongside Amazon, Apple, Facebook, and Google in Silicon Valley. “We need to innovate outside of Korea with Silicon Valley,” Sohn concluded.

Rounding off the keynote presenters was Martin Lund, Senior VP of the SoC Realization Group at Cadence. He explained that, while SoCs were everywhere from smartphones to the cloud, the new thing was the growing application space in which these chips must exist.

Cadence’s Martin Lund (center) talks with editors Ed Sperling (right) and John Blyler (left) about the next generation of IP technology. (Photo courtesy of Lani Wong)

Lund focused on the design of the SoC, but with this twist: The application space for chips is growing to encompass the Internet-of-Things universe – from smartphones and new application devices to the cloud.

A key challenge presented by expanding application spaces was the IP verification of ever-changing standards. “There are hundreds of pages of requirements for just the latest PCIe, Gen. 3 specification,” he noted. “All of these dynamic requirements affect the IP on the SoC.”

The traditional idea of IP reuse was that once IP was created, it could be reused over and over again. Lund said that this idea was being challenged. He used the evolving Ethernet standard as an example, where 45 cumulative additions had occurred since the standard’s origin in 1983. Such constant changes meant that the IP-reuse model was under stress.

To meet this challenge, IP must be designed for change. He explained that IP must be optimized for the application (i.e., from a software perspective). This approach also addresses the fact that software often decides if a design will achieve the critical time-to-market (TTM) window.

IP must be built to fit the SoC. To achieve this end, Lund said that next-generation IP must be optimized for the end application. It also must be part of an intelligent subsystem. Furthermore, IP must be pre-verified. This is why Cadence provides a growing number of design cores and verification IP tools, he concluded.

For more details, read Richard Goering’s blog: Martin Lund CDNLive Keynote: Why SoCs Need “Application Optimized” IP.


Related coverage and reference content:


Originally published on “IP Insider.”

John E. Blyler
Author, IP Insider blog
Editor-in-Chief, Chip Design magazine

Free counter and web stats

Semiconductor Leaders Respond at Common Platform Technology Q&A

Friday, March 8th, 2013

Will Extreme Ultraviolet (EUV) lithography ever come to pass? When will nanotube technology hit the market? Will the cost of chips continue to go down? These were just a few of the questions covered during the press lunch at the 2013 Common Platform Technology Forum. The panelists included (seated, left to right): Michael Cadigan, General Manager of IBM’s Microelectronics Division; Gary Patton, VP, IBM’s Semiconductor R&D Center; KH Kim, Executive VP for Samsung Electronics’ Foundry Business; and Mike Noonen, Executive VP of Global Sales and Marketing for GLOBALFOUNDRIES. What follow are excerpts of that discussion.

Question: When will nanotube technology hit the market?

Patton: FinFET structures will last a decade, maybe longer. Moving beyond silicon to III-V materials will also help to extend existing designs. (Editor’s note: The III-V compound semiconductors come from combining group III elements (essentially Al, Ga, and In) with group V elements (essentially N, P , As, and Sb) of the periodic table. This results in 12 possible combinations. The most important ones are probably GaAs, InP, GaP, and GaN.)

Question: Will EUV ever come to pass?

Patton: EUV requires real physics changes. At the recent SEMI Industry Strategy Symposium (ISS), someone said that EUV is hard work. No, it is hard physics. The industry is trying to extend immersion and double patterning, but  no one wants to move to quadruple patterning.

Question: What does “hard physics” mean? The scientific effort is 20% while the engineering portion is 80%?

Patton: I’ve never attached a percentage to it. Perhaps it would be 60% science and 40% engineering effort.

Cadigan: We had envisioned the entry point for EUV at the 10-nm-node geometry. Now, that point is 7 nm. If anyone has seen ASML’s EUV tool, they know it’s really tough.

Question: If you don’t have EUV at 7 nm, will you need triple or quad patterning?

Cadigan: Yes, we always have an alternative. For example, fully depleted (FD) silicon-on-insulator (FD-SOI) was ready at about the same time as FinFET technology. If FinFET had been late, FD-SOI was the backup plan.

Question: Costs continue to rise for chip design and manufacturing. Will Moore’s Law end soon?

Noonen: Cost is where the rubber meets the road. Fabs must make money, but need to offer designers the right mix of power, performance, and cost (i.e., they must right-size to the right solutions). This goes beyond one metric, beyond a geometry.

Question: Lowering the cost of chips is a maturation of process. Is that maturation taking more time?

Noonen: We are working on 28-nm to 14-nm geometries all at once, accelerating the process to bring forth multiple nodes. This is breaking the typical two-year duty cycle between nodes from previous years.

Cadigan: I use the phrase time-to-market (TTM) instead of maturation. Our partners want earlier involvement to bring their technology to market at a faster pace. The model is shifting in 2013 – we all must work faster. For us (IBM), that shift means moving more quickly from the Albany facility to Fishkill to our customers to shorten the time for development – and hence TTM.

Science is nice, but cost is critical. We need to drive the cost out of the technology. For example, we are leveraging what we learn in Fishkill – which is not high-volume –  along with Globalfoundries and Samsung to leverage the total cost point.

Question: Will 450-mm wafers be available in the latter part of this decade?

Cadigan:  The Global G450 Consortium now has a consensus that 450 mm is happening. But I don’t know the timing of 450 mm. Volume production will probably come at the end of the decade. The challenge is that the timing of 450-mm wafers will depend upon lithography technology – back to the EUV question. But EUV will come to market for both 300 mm and 450 mm (see “CNSE Readying NFX Fab for G450C, EUV Efforts”).

Question: Will the tools at 10 nm reduce the need for triple and quadruple patterning?

Patton: We’ve extended immersion for a long time. Programmable light-source work is ongoing with ASML. Directed self-assembly (DSA) could be used to avoid quadruple (4) patterning.

Question: Broadcom’s CEO is quoted as saying that the benefits for cost on scaling will not continue. Cost benefits of scaling have gone away. Do you agree?

Patton: Comparisons between 20-nm to 14-nm nodes are not good, since those are not full nodes. You need to compare cost scaling between full nodes. In the past, 50% scaling provided 20% cost savings. Those ratios will change.

Question: The original idea of the Common Platform Alliance was to share fabs. Is that still possible?

Cadigan:  That was the original idea – release a design into two different fabs using the same kits (PDKs). As we evolved, we realized that only a few companies would do that. Samsung will tune its process slightly off of our common platform base. Or Globalfoundries will have one or two large clients who want a tuning. Our goal is still common-based foundational content. Now, it’s okay to personalize it.  That’s why we are doing more in Albany instead of Fishkill.

Free counter and web stats

Flexible Yogurt-Lid Electronics Become a Reality

Friday, March 1st, 2013

Truly flexible electronics from processor, memory, interface, and battery components are here, thanks to Intel, IBM, STMicro, Leti, Imec, Kaist, Kovio, and others.

As leading-edge semiconductor companies race toward ever-smaller, atom-sized chips, it’s easy to overlook the amazing advances made in higher nodes – especially in plastic and organic electronics. This is good news for the chip design community, as the implementations of flexible and organic electronics will renew interest in existing semiconductor intellectual-property (IP) designs.

Earlier this year, Intel Labs, Plastic Logic and Queen’s University announced joint work to create a “paper” tablet computer. Developed at Queen’s University, the flexible tablet called “PaperTab” looks and feels like a sheet of paper. It is powered by a second generation Intel Core i5 processor. Unlike today’s tablets where several apps or windows can appear on the single display, the PaperTab would have one paper per applicatio but users could have several displays – like pages in a book.

For example, IBM recently demonstrated a thin-film-like flexible circuit that resembled a “yogurt lid.” This extremely flexible film, which is rooted in a silicon-on-insulator (SOI) -based plastic substrate, contained nearly 10,000 transistors. Adele Hars, Editor-in-Chief of Advanced Substrate News, described it as follows: “IBM has developed a new, low-cost technique that starts with the Full-Depleted (FD)-SOI technology developed with ST and Leti, for manufacturing silicon-based electronics on a flexible, plastic substrate. IBM’s Gary (Patton) showed a sample (at CPT 2013), and said that ‘research suggests that flexible, affordable electronics can be made with conventional processes at room temperature.’”

IBM’s flexible electronics and related semiconductor advances were part of my brief conversation with Sean O’Kane from Chipestimate.TV: Common Platform 2013 – Walk and Talk – Sean O’Kane and John Blyler (Part 1).

Of course, it will take more than just a processing circuit to create viable commercial products from flexible and organic materials. What about a memory system, interfaces, and power source? All of these other components are now available:

Imec’s Organic Processors Offer Microwatt Applications

Printing low-power, low-performance microprocessors onto organic materials will open a wide range of cost-effective alternatives to traditional silicon wafers.

Memory Challenges In The Extreme

Another example of an extremely low-power, low-performance memory application is in the emerging market of flexible, plastic electronics.  A team from the Korea Advanced Institute of Science and Technology (KAIST) recently reported such a device [i.e., a fully functional, flexible, nonvolatile, resistive random-access memory (RRAM)].

Kovio’s near-field communications (NFC) wireless tag is created using electronic inks and industrial graphics printing tools instead of more expensive ICs on silicon wafers.

Stretchy Battery Drawn to Three Times its Size

Researchers have demonstrated a flat, “stretchy” battery that can be pulled to three times its size without a loss in performance.

As consumers, the age of flexible, “yogurt-lid” electronics may finally be here. With these advances, everything from our clothes to cereal boxes may serve as personal computers and communication systems.

Free counter and web stats