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Modular FinFET Increases Planar-to-Non-Planar IP Reuse

At IEDM, Globalfoundries explained why its 14-nm-class Fin with a 20-nm back-end combination would increase planar IP portability to non-planar FinFETs.

Often, the best questions are asked and answered after the main event. A case in point was the press roundtable that convened after Globalfoundries CEO Ajit Manocha’s luncheon keynote during the 2012 International Electron Devices Meeting (IEDM). Manocha (center seat) was joined by the following senior executives: Suresh Venkatesan (left seat), Senior Vice President of Technology Development, and Subramani Kengeri (right seat), Vice President of Advanced Technology Architecture (see Figure 1). What follows is an edited version of that question-and-answer session. – JB

 

Figure 1: Pictured are the Globalfoundries CEO and senior executives at the IEDM press roundtable. Jason Goross, Communications Manager, is shown standing.

Question: What about new technologies, like Extreme-Ultra-Violet (EUV) lithography and directed self-assembly?

Manocha: We’re working on EUV technology as well as immersion scanners for double patterning (see Figure 2). The jury is still out on commercial EUV, especially since suppliers remain 9 months or so out.

We are not working on directed self-assembly (DSA; a manufacturing process to improve both optical and EUV). Thus far, it is not a prime consideration for 7-nm-node technology. However, we have been talking with KLA-Tencore as part of our open collaboration approach to deciding the right thing to do.

As I mentioned in my keynote, at least one big company (IDM/foundry) is under 50% utilization capacity. We need a way to keep it going by living on 28-nm with silicon-on-insulator (SOI) and other technologies.

Figure 2: In his IEDM 2012 keynote, Globalfoundries CEO Ajit Manocha talked about the challenges facing the semiconductor manufacturing industry.

Question: Is Globalfoundries FinFET-friendly?

Manocha: We are mitigating the risk of mobile systems-on-a-chip (SoCs) by incorporating a 20-nm back end with a 14-nm front end.

Kengeri: Globalfoundries wants to leverage all of its 20-nm investment. That includes reusing models on the technical side. For example, there are 7000 ground rules. We want to carry those rules over, only changing the device. On the design side, people are used to 20-nm design rules. We want to keep that design infrastructure.

Editor’s Note: As announced in Sept. 2012, GlobalFoundries is taking a “modular Fin” approach with its bulk FinFET offering, dubbed 14nm-XM (see Figure 3). This approach combines a 14-nm-class Fin with its 20-nm back-end-of-line (BEOL) interconnect flow. It includes  ‘Fin-Friendly Migration’ (FFM) rules to allow the fast porting of planar intellectual- property (IP) designs to FinFET. The company predicts 40% to 60% improved battery life and 20% to 55% higher performance (depending on operating voltage) vs. other 20-nm, 2D planar transistors. (See “GlobalFoundries Rolls Out 14nm finFET Process.”)

Figure 3: Shown is Globalfoundries' 14nm-XM FinFET structure.

Question: Regarding the IP side, won’t changing the device cause changes in the IP?

Kengeri: Yes, we do need to redo the IP (for 14nm-XM), but not as much as before.  We don’t need the 2x change that is traditionally needed between major node jumps. There is where the ecosystem engagement comes in. The IP is being designed because the 14nm-XM design kit (PDK) is already complete.

In addition, there is concurrent IP development within our ecosystem (e.g., ARM), since the physical design rules are already there.

Venkatesan: Let me add a quick comment. We have done the physical design, electrical characterization, and optimizing of the IP.  The physical design rules for 20 nm are complete, so the IP development has started. IP developers can be assured that no big changes will happen. There may be changes in the electrical characteristics, but that just needs retiming, etc. – not the same level of pain and suffering as the PDK development. [Note: The PDK contains descriptions of the basic building blocks of the process including FinFET (Spice) models, advanced extraction,  double patterning, DFM, FFM, Ref flows, P&R…]

Editor’s Note: In this short video, Sean O’Kane from Chipestimate.TV and I talk with ARM’s John Heinlein about the coming challenges faced by IP designers using FinFET structures.

TSMC OIP 2012: ARM’s John Heinlein is interviewed about IP and FinFETs.

Originally published on “IP Insider.”


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