Virtual Reality for Chip Design?
As chip design moves into the realm of three-dimensional transistor structures and even MEMS, virtual-reality simulators may prove a necessity for both architects and educators.
They say that travel broadens the mind. That has certainly been the case with my recent visits to some of the leading semiconductor and electronics tool companies and research organizations in Europe, including ASML, Dassault Systemes, and Imec. Each of these entities offers technologies that are pertinent to the IP community, which I’ll cover in the coming weeks.
For now, let me whet your interest with a short video clip from Dassault Systemes’s virtual-reality development and deployment system, which is called 3DVIA. Think of it as a super-fast and detailed simulation program expanded into three dimensions.
Such a system might seem like overkill for the world of chip design. After all, EDA-IP tool providers already offer sophisticated modeling and simulation tools for every aspect of chip design – especially in virtual software through hardware-based prototyping. Still, as the chip community moves into an era of 3D structures, through-silicon vias (TSVs), stacked dye, and microelectromechanical (MEMS) devices, the potential benefits of virtual-reality (VR) simulation become more tangible. Such VR simulations could be used to visualize the effects of evolving transistor structures, such as fin-Fetts, or to enhance the accuracy of thermal flows around stacked die. Plus, 3D and virtual-reality models have proven invaluable as teaching aids to both novice and seasoned designers across a wide range of engineering disciplines.
Translating the complex interactions of today’s systems-on-a-chip (SoCs) into a virtual-reality program would require serious processing and graphics hardware. Each dimensional display in the 3DVIA system requires at least one server and GPU cluster. Fortunately, advances in server and GPU technology make these systems available on the commercial market.
Like the EDA industry, chip design must become part of a larger system-design process – both in terms of disciplines (EE-CS-ME) and domains (chips-boards-modules). The move toward a system view necessitates additional simulation and modeling tools. Virtual reality may have a strong play in this evolving world.