SOI Parity with CMOS Good News for IP Designers
Soitec panel at Semicon West challenges both the IDM model and the dominance of bulk CMOS as material of choice for chips at 20 nm process nodes.
(Originally posted on “IP Insider“) During Semicon West 2012, Soitec hosted a panel and celebration event to mark their 20th anniversary. The company and the Silicon-on-Insulator (SOI) industry as a whole had a great deal to celebrate with the onset of 20nm process node technology for System-on-Chip (SoC) design.
At the 20nm node, companies are looking to fully depleted (FD) SOI to match or even exceed parity with bulk CMOS in many areas, including power and physical effects. This parity, as applied to the future of mobile computing, was the subject of a lively panel that preceded Soitec’s celebration event. The panel consisted of well-known experts from UC Berkeley, IBM, ARM, GlobalFoundries, STMicroelectronics, the SOI Consortium and Soitec. (see, “SOI Becomes Essential At 20nm”)
Why is SOI finally a real alternative to bulk CMOS at 20nm? A recent SOI Industry Consortium benchmarked 28nm bulk vs. 28nm FD-SOI to compare silicon with similar processor (ARM) and memory controller IP blocks. The comparisons demonstrated that FD-SOI was comparable with the leakier ‘General Purpose’ technology, at better dynamic power, and dramatically better leakage power. (STMicroelectronics has a white paper )
What would be the impact to semiconductor intellectual property (IP) designs that move to fully depleted two-dimensional (FD-2D) SOI from traditional CMOS chips? Negligible, explained Steve Longoria, SVP of global strategic business development at Soitec. The FD-2D process uses existing IP libraries and design tools, so no changes in any of the fabless companies IP are needed. Further, Longoria notes that FD-2D is compatible with planar CMOS production lines, which mean no new equipment costs or retaining of staff.
Will the advantages of FD-SOI spell the end of bulk CMOS at lower process nodes? Probably not, as designers find new ways to work around power leakage and other challenges. But having an alternative should only encourage more innovation in the race to keep pace with Moore’s law.
Soitec’s 20th Anniversary Event in Pictures and Tweets
(Post during the event by jblyler @Dark_Faust)
- “20nm complexity means partners must collaborate early on” -Subramani @GLOBALFOUNDRIES @Soitec_FD #semieda @Chip_Design #MobileatMOMA
- FD planar: “In mobile, power is key. Performance added as headroom allows.”- Moore from @ARM @Soitec_FD #MobileatMOMA
- Vertical dimension critical for Finfett. SOI has advantage at lower nodes. – Patton from @IBM @Soitec_FD @Chip_Design pic.twitter.com/6dTnNsCG
- Old partially depleted issues are gone. SOI now looks like bulk CMOS. – Mendez from @soiconsortium #MobileatMOMA pic.twitter.com/tKvVv3NR
- Fully depleted SOI now an SOC worthy alternative to bulk CMOS. – Magarshack from @STMicroelectronics #MobileatMOMA pic.twitter.com/SkA7fSZR
- Soitec 20th Anniversary! CEO Auberton-Herve speaks. #MobileatMOMA @Soitec_FD #semieda @chipestimate @Chip_Design pic.twitter.com/k49oK873