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DDM and PLM Tools Challenge Semiconductor IP Reuse

Recent data suggests the value and shortcomings of design data management (DDM) and project lifecycle management (PLM) tools to improve IP reuse.

Last time, I focused on the potential long revenue tail of chip design afforded by the extraction, packaging and selling of semiconductor IP. IPextreme is one example of a company that enables the extraction, package and creation of licensable IP products. Websites like the GSA portal, IPestimate’s Constellation platform and Chipestimate.com can help with the distribution and potential sales – among other things.

Yet all of these companies with the exception of Chipestimate.com live outside the realm of the chip development process. Chipestimate.com provides estimation tools like InCyte Chip Estimator and Cadence Chip Planning System (CCPS) that allow designers to make IP tradeoffs in terms of power, performance and even cost. But who can help manage the actual process of chip design?

The answer lays in the world of design data management (DMM) tools, a broad category that encompasses such companies as ICManage, Cliosoft, Methodics, Numertrics, Satin Technology and others. Reaching to even higher levels of design abstraction is software-hardware tools aimed at complete system-level development. (That’s a discussion for another day – or perhaps a month of days.)

Let’s return to our level of abstraction of the chip design and semiconductor IP creation. A recent study found that one of the top factors driving the use of chip-level design management systems is “IP Reuse/Logistics Management (43%).” This data comes from the annual Global Design Management report sponsored by ICManage. Further, the year-over-year data suggests that improved IP reuse and logistics management continue to be illusive goals for most SoC developers.

The report also found shortcomings in existing tool offerings by noting that the most critical feature for IP reuse/logistics management is bug notification and tracing (50 %), followed closely by integrating and assembling the IP in the design (48%) and efficiently making internal IP available for reuse (47%).

Regardless of the shortcomings, any tools that can help manage the growing complexity of the chip design and IP reuse processes are welcomed in our industry.

References:

  • Collaboration Penalty Is Steep For Engineers - System-Level Design sat down to discuss chip-design productivity and quality issues with Srinath Anantharaman, president and founder of Cliosoft; Ronald Collett, president and CEO of Numetrics Management Systems; and Michel Tabusse, CEO and co-founder of Satin Technologies.
  •  The IP Blame Game - The topic of IP quality in the SoC era is difficult to define, and solutions to problems relating to IP quality, verification, and use are hard to find. Debates rage between IP users, suppliers, and EDA vendors about where the responsibility lies for making quality IP available for use and re-use in an efficient, predictable, and scalable manner.
  • EDA Extends Board Design into Manufacturing - A recent EDA and PCB acquisition represents a significant merger between the worlds of electronic and mechanical manufacturing.
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Originally published on Chipestimate.com “IP Insider”

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