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Archive for January, 2012

Venture Capitalists see Major Investing Changes

Thursday, January 26th, 2012

At the recent AO Venture Summit,Silicon Valleyinvestors cautioned about changes to traditional investment funding models as the semiconductor market enters a cyclical downturn.

At the 2012 World Economic Forum held atDavos,Switzerland, financial leaders from around the world worry about the future of capitalism. As wealth disparity and the thread of a global recession stalks the planet, few would argue that fundamental financial changes are taking place.

One bright spot in the economic gloom is the semiconductor industry, which has experienced strong growth in recent years. But this is an industry prone to cycles that are tied closely to enterprise and consumer consumption, were the former seeks production efficiencies while the latter seeks social connectivity.

Reports suggest that this bright spot will dim slightly as the semiconductor industry enters a down cycle.  Earlier this month, speakers at the SEMI Industry Strategy Symposium (ISS) trade show predicted a chip downturn in 2013. Global foundry giant TSMC pegs the slowdown closer to 2012.

How will these changes affect the flow of investment dollars into Silicon Valley, the center of innovation for the semiconductor market? A recent panel at the AlwaysOn Venture Summit suggests that fundamental changes to the investment funding model may have a greater affect than the ongoing global financial crisis.

Venture Capital Business Outlook 2012 panel at AO Venture Summit.

What follows is a portion of a panel on the venture capital business outlook for 2012.  The host was Packy Kelly, Partner and Co-Head, US Venture Capital Practice at KPMG. Panelists included Ann Winblad, Co-founder & Managing Director at Hummer Winblad; Rob Chaplinsky, Managing Director at Bridgescale; and Paul Matteucci, General Partner at USVP.

The moderator, Packy Kelly from KPMG, started the discussion by observing that the 2011 venture capital industry was disrupted by over-funding in both the Angel and Late-Stage venture investment rounds. Lower amounts were being raised by VC firms than were being invested. He asked the panelist for their thoughts on the shape of the competitive landscape for venture capital investing in 2012.

First to answer was Ann Winblad from Hummer Winblad. She began by stating that her clients were unlimited investors that were used to longer investment cycles. To date, most venture funds try to get completed in a 10 year cycle, with a company going public after 6 years. Today things are different. She wondered if unlimited partners had the endurance to go for a longer investment cycle.

There have been many expansions and contracts of this cycle over the years. “The expansion in the 1990’s was as scary as the contractions,” said Winblad. Still, the asset class is performing well. Today, most companies don’t have an IPO exit strategy. Instead, they are looking for acquisitions. Winbald explained that she had 6 companies acquired in last year – something that hadn’t’ been anticipated. But it was good news for the venture industry. Business as usual is now over a longer period of time.

Next to comment was Paul Matteucci from USVP. He agreed that the investment cycle was taking much longer times to equity, which meant that patience and staying power are critical. Since his focus was IT, he was excited about the growth of device location technology over next 5 years. “Lots of investment will be driven by these trends, including in the medical market,” explained Matteucci.

Another growth market for location technology would be agriculture. The problem with that market was knowing when to start. You don’t want to start too soon or you’ll lose, said Matteucci, adding that the agriculture market looks like the IT industry in the 1970s.

Finishing this first round of questions was Rob Chaplinsky from Bridgescale. He felt that the current trend of investment money pouring into deals but not funds was unsustainable. A new type of venture capital approach was needed, perhaps with a greater emphasis on startup incubators. “Now, I’m not so skeptical on incubators,” said Chaplinsky. His firm had 40 companies working as incubators, most doing software programming. The average age in the incubator coders was 23-24 year olds. These people are fearless and full of energy, believing they were geniuses and with little patience for non-programmers, he observed. The challenge for VCs with these types was to develop trust early on.

On the business side of things, Chaplinsky felt that his clients see greater risk in Series A and B stages of investment. Most of them want later stage deals, further into actual product deployment. This was one sign that the VC market is going through massive changes.

 

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Carbon’s Exchange Bolsters Front-end IP Chain

Tuesday, January 17th, 2012

Today’s announcement of Carbon’s IP Exchange portal provides evidence of the growing importance of the semiconductor IP design-manufacturing chain.

The third-party IP development chain gains additional support with today’s introduction of Carbon’s IP Exchange portal. According to Bill Neifert, Carbon’s CTO, “the portal is focused on the front-end of the design process to enable virtual platform creation and execution.”

Neifert describes the process as straight-forward: a designer logs into the portal, chooses the IP of interest and configures the block with vendor supported parameters. IP Exchange then automatically compiles a virtual model for that IP block and makes it available for download.  The model is retained on site for use by other team members or for later reconfiguration.

A few months back Synopsys introduced “TMLCentral” – another tool to aid in the front-end IP design activities. Rather than containing any information on IP blocks, the site provided transaction-level representations of IP – a valuable resource to SystemC users. According to Tom De Schutter, senior product marketing manager at Synopsys, “TLMCentral focuses solely on transaction-level modeling and virtual prototyping methodologies.”

Both of these front-end tools – Carbon’s IP Exchange and Synopsys’s TLMCentral – are complementary with the Cadence’s Chipestimate.com (CE) site. Using designer selected IP, CE’s estimation tools provide trade-off analysis for a variety of backend effects, such as power consumption, die size and even cost. But the CE tools are also used early in the design process where system-wide architectural power and performance trade-offs are examined.

All of these IP portals strengthen the ability of System-on-Chip (SoC) designers to develop and integrate third-party blocks into ever complex designs. The recent introductions of front-end specific IP tools are complementary to existing architectural and back-end offerings. Together, these tool suites re-enforce the growing importance of a healthy IP ecosystem in the design of today’s semiconductor chips.

Originally posted on Chipestimate.com

IP Trumps Moore’s Law in SoC Costs

Wednesday, January 11th, 2012

Apple continues to reduce system costs through customized chip design via IP integration and software tailoring, not through traditional cost per gate.

No one doubts the intrinsic value of design reuse via third party semiconductor intellectual property (IP). Incorporating IP of known quality into a chip design allows companies to concentrate on their core design competencies while adding all the other functionality required for today’s complex System-on-Chip (SoC) integrated circuits. Large ecosystems of third party IP suppliers exist to fill this need within a royalty-based business model.

A large company can gain additional advantages over the royalty-based model through outright ownership of critical IP. Acquisition of IP allows a company to customized the IP to meet specific design needs or processes, e.g., such as low-power. Further, acquisitions give a company access to valuable technical IP in the form of engineers and process professionals. Finally, acquisitions may afford a strategic advantage to a company, allowing them to limit competition to key IP technology.

In practice, large companies follow both approaches to varying degrees. For example, ARM acquires IP companies as necessary but focuses much of its energy on building and supporting the third-party ecosystem.

Intel has recently begun in earnest to emphasize the development of its IP ecosystem – mainly consisting of companies it had acquired. (see, “Intel Challenges ARM with IP and Interconnect Strategy”)

Recent news shows that Apple follows the same approach of customizing its design chain through the IP acquisition.  Apple’s recent purchase of Anobit adds memory controller expertise to the company’s existing low-power microcontroller (PA Semi) and DSP (Integrity) portfolios.

However IP is obtained – through royalties or acquisitions – it is the game changer. “In the SoC era, system performance and development costs are not dominated by cost per gate (Moore’s Law) but rather chip design and software,” said Gus Richard, an analyst with Piper Jaffray & Co., in a report, which was obtained by SemiMD. (see, “Apple Buying Anobit as it Builds IP Portfolio,” by Mark LaPedus)

“The (Apple) A5 processor is not faster than an Intel processor, but instead it has a large number of IP blocks that execute functions with lower power and typically more quickly than a general purpose CPU. We believe that the CPU is only a portion of the SoC and has become less relevant,” he said. “This coupled with the fact that Apple’s software is written to work with one set of hardware resources significantly reduces software development cost as compared to Windows that needs to run on an infinite combination of hardware resources.”

This tight coupling between chip customization and software is replacing processor performance as the critical design driver. While this realization is nothing new, the technical reality continues to play out in a shift to subsystem rather than component IP development. Augmenting this shift to subsystem IP are the business realities of a slow global economic recovery and the very large cash reserves of many tech companies. All of which suggests that IP-based acquisitions will increase in the near future.

(First appeared in Chipestimate.com – IPInsider)

Time Cloak for Digital Logic?

Friday, January 6th, 2012

Time cloaking has been demonstrated using light waves. What might that mean for particle models, as in IC applications?

Here’s a mental exercise for circuit designers. It evolves the application of a time cloak to electron particles in a digital circuit. But first, a bit of background information might help.

 Temporal cloaking allows researchers to change the perception of time. I reported on this amazing experiment last year.  (see, “Time Travel is Out: Stopping Time is In”)  

 A team of physicists at Cornell University created a time gap by briefly bending the speed of light around an event – not an object. The experiment involved changing the speeds of different light waves. The gap lasted only 50 trillionths of a second. A scaled up version of this demonstration shows an art thief walking into a museum to steal a painting without setting off laser beam alarms or even showing up on surveillance cameras. 

The time gap was demonstrated through the use of light waves. But quantum phenomena can be modeled as either waves or particles. How would a time cloak work in a particle representation?

The key to the Cornell experiment was the changing speed of different wavelengths of light. A corresponding particle representation might involve changing the speed of  electron “particles.” But electron motion is at best a statistical measurement, if one applies Heisenberg’s uncertain prediction for momentum and position.

Before exploring this challenge further, one might wonder as to the practical use of time cloaks. What could they be used for? In a circuit, the faster flow of electrons might cause an unintended output from a given set of logic functions. This assumes that the transistors could switch fast enough to operate with higher speed particles. Silicon transistors may not work, but there is an alternative.

Recent reports from IBM show that graphene switches can reach speeds of 100 gigahertz–meaning they can switch on and off 100 billion times each second, about 10 times as fast as the speediest silicon transistors. That should be fast enough for our theoretical time cloak particle experiment.

The next challenge is to create a circuit with two logic flows – one for normal speed and another for faster electrons. The faster electrons would complete their logic functions before the “normal” logic was finished. To what end, you ask? Perhaps to completely disable the rest of the circuit? This might be a problem if the circuit was part of the communication system for a fighter jet.

Of course this scenario is not that new. Many have suggested that RTL could be added to circuits just prior to fabrication in a foreign foundry to achieve the same dangerous result. (see, “Foreign Fabs and Killer Apps”) But with a time cloak, the “hidden” circuit would not be hidden at all or even added in secret. It would be there for all to see but completely undetectable except when the “time cloaked” faster electrons were activated.

Unfortunately, this scenario of a particle-based, digital time cloak is fatally flawed. An astute first year student in engineering would be able to spot the flaw in short order. Can you?

I’ll post my answer in the next blog.