R&D Focuses on Low Power and Stacked Die
By John Blyler
This is an important story that I meant to cover earlier.
One evening last month at DATE, a reception marked the opening of Atrenta’s new research and development facility located at the Micro and Nanotechnologies Innovation Center (MINATEC) campus (see Figure 1). Atrenta had been involved with MINATEC for over 10 years. That relationship was strengthened with the hiring of several Ph.Ds on the campus. These additional professionals will be part of the Atrenta R&D team in Grenoble.
The DATE reception was sponsored by both Atrenta and CEA/LETI, the electronics and information technology laboratory of the French Atomic Energy Commission. The R&D effort will focus on EDA software tools in the emerging markets of advanced power reduction and 3D stacked die design.
The speakers at the reception formed a veritable “Who’s Who” of the European electronics industry (see Figure 2).
I couldn’t attend DATE this year, held in Grenoble, France. I’m told that the MINATEC center is located in the northern part of the city with spectacular views of Alpine mountain peaks.
Peggy Aycinena, a fellow editor who did attend DATE, provided a complete and colorful description of the Atrenta and CEA/LETI event on her “Superheros of SoC” site: “Atrenta Inaugural in Grenoble”