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ASIC and ASSP Prototypes Accelerate Below 65nm

One time-honored way to achieve the ever conflicting trade-off between high performance and low power is by manufacturing ASIC designs at a lower process node. This approach works especially well with digital circuits, which scale more easily to lower nodes than their analog brethren.

One indicator of this trend toward lower manufacturing geometries is the shrinkage of the process node of current and future FPGA-based ASIC prototypes. Designers use such hardware prototypes to architect and verify the newer or more troublesome portions of their latest leading-edge chip designs.

Currently, the trend is toward prototypes targeted at designs below 65nm (see Figure 1). This trend is hardly surprising. Early in 2010, Xilinx announced that their latest generation of FPGAs was manufactured at the 28nm process node. On the processor side, Intel recently announced the building of a new 22nm fab in Oregon.

Figure 1: Three-year trends in manufacturing process nodes for current ASIC/ASSP/SoC prototypes based on FPGAs. (CDT Survey)

Perhaps of greater interest is the rapid movement in chips designs planned at below the 65 nm process node.  In a 2010 survey, when ASIC designers were asked for the target process nodes for planned ASIC/ASSP/SoC prototyping designs, an overwhelming majority listed “Below 65nm.” (see Figure 2)

Figure 2: Three-year trends in manufacturing process nodes for planned ASIC/ASSP/SoC prototypes based on FPGAs. (CDT Survey)

This 2010 increase in “Below 65nm” designs represents a substantial increase from the previous two years. It also confirms an increase in capital expenditures for the new semiconductor equipment needed to support the lower process geometries. For example, Gartner recently reported that semiconductor equipment spending grew by a record 131% in 2010. Early predictions are for the spending to be flat in 2011, in part because the new systems are now in place. Equipment purchases in 2011 should focus more on capacity than supporting the latest technology node. 

FPGA chips continue to become ever smaller in size, lower in power while denser in transistor count and hence end-user functionality. To achieve these capabilities, chip manufactures must upgrade or replace existing equipment to systems that support the latest process nodes. Data from a number of different sources confirms that this is the phase of the chip manufacturing life cycle that exists today. We can look forward to more products designed to below 65nm process nodes in the near future – at least in the digital world.

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