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Archive for January, 2011

Nanometer Chips Blend Work on Quantum Affects and Light

Friday, January 28th, 2011

For all you science geeks out there, consider this blog as my chip and quantum computer design “weird science” update. [Weird because quantum mechanics is weird … cool weird, but still weird.]

Today’s electronics are based upon a flow of electrons. Conversely, quantum computers will use photons or particles of light instead of electrons. One of the first steps in building a workable quantum computer is to create an on-demand photon generator. Two recent papers by The National Institute of Standards and Technology (NIST) scientists define a mechanism for creating and delivering such photons. In their works, these scientist describe not only how to produce a steady flow of photons but also how to do so one at a time and only when needed by the computer’s processor. (see Figure 1)

Why build a quantum computer in the first place? The reason is simply that such systems could perform calculations that are impossible using conventional computers by, “taking advantage of the peculiar rules of quantum mechanics.”

For more developments on quantum computers, see: “Quantum Computers Move A QuBit Closer To Reality

Figure 1: Gated photon source starts with the bright green laser beam that strikes a crystal and is converted into pairs of photons (false colored blue here, it’s at the end of the red spectrum) and (in the infrared, false colored red here.) The “blue” beam is the herald channel, the “red” beam goes through a spool of optical fiber (right) to delay it long enough for the gate to open or shut. Credit: Brida, INRIM

 

Optical systems, like their quantum brethren, are also based on light. Since nothing that contains any information can travel faster than the speed of light, the medium makes an ideal candidate for high-bandwidth interface I/Os between deep-submicron CMOS chips. The curious thing is that deep-submicron chips are now designed at the nanometer level, where the effects of quantum mechanics begin to actively affect the flow of electrons.

Isn’t it interesting how the two worlds of quantum mechanics and light keep impinging on one another?

IMEC, the world’s leading-research center in nanoelectronics, has just launched a new research program aimed at high-speed, high-bandwidth optical interfaces for communication between chips. If anyone can shine some light onto this problem of achieving mind-boggling communication speeds between integrated circuits, it’s IMEC.

Figure 2: Silicon-photonics wafer processed at IMEC’s fab.

ASIC and ASSP Prototypes Accelerate Below 65nm

Thursday, January 13th, 2011

One time-honored way to achieve the ever conflicting trade-off between high performance and low power is by manufacturing ASIC designs at a lower process node. This approach works especially well with digital circuits, which scale more easily to lower nodes than their analog brethren.

One indicator of this trend toward lower manufacturing geometries is the shrinkage of the process node of current and future FPGA-based ASIC prototypes. Designers use such hardware prototypes to architect and verify the newer or more troublesome portions of their latest leading-edge chip designs.

Currently, the trend is toward prototypes targeted at designs below 65nm (see Figure 1). This trend is hardly surprising. Early in 2010, Xilinx announced that their latest generation of FPGAs was manufactured at the 28nm process node. On the processor side, Intel recently announced the building of a new 22nm fab in Oregon.

Figure 1: Three-year trends in manufacturing process nodes for current ASIC/ASSP/SoC prototypes based on FPGAs. (CDT Survey)

Perhaps of greater interest is the rapid movement in chips designs planned at below the 65 nm process node.  In a 2010 survey, when ASIC designers were asked for the target process nodes for planned ASIC/ASSP/SoC prototyping designs, an overwhelming majority listed “Below 65nm.” (see Figure 2)

Figure 2: Three-year trends in manufacturing process nodes for planned ASIC/ASSP/SoC prototypes based on FPGAs. (CDT Survey)

This 2010 increase in “Below 65nm” designs represents a substantial increase from the previous two years. It also confirms an increase in capital expenditures for the new semiconductor equipment needed to support the lower process geometries. For example, Gartner recently reported that semiconductor equipment spending grew by a record 131% in 2010. Early predictions are for the spending to be flat in 2011, in part because the new systems are now in place. Equipment purchases in 2011 should focus more on capacity than supporting the latest technology node. 

FPGA chips continue to become ever smaller in size, lower in power while denser in transistor count and hence end-user functionality. To achieve these capabilities, chip manufactures must upgrade or replace existing equipment to systems that support the latest process nodes. Data from a number of different sources confirms that this is the phase of the chip manufacturing life cycle that exists today. We can look forward to more products designed to below 65nm process nodes in the near future – at least in the digital world.