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Scalable Architectures Expand into FPGAs

Moore’s Law assures us that the transistor count of IC devices like FPGAs, ASICs and ASSPs will double every two years – with each successive process node. This means that chip density or capacity will increase and power consumption per transistor will go down.

Still, the numbers for Xilinx’s upcoming 28nm Virtex-7 family of FPGAs are impressive: 50 percent power reduction and more than doubling of the logic cell density (now at 2 million) over its 40 nm Virtex 6 devices.

Aside from improved power, performance and device capacity, the new 7 Series FPGAs offers scalability across the full family of devices. In previous generation of FPGAs, scalability was limited to within a family of devices, such as within the 40nm Spartan or 45nm Virtex-6 families.

This scalability is the result of the company’s unified FPGA architecture in which all of the 7 series devices use the same building blocks (logic fabric, Block RAM, clocking technology, DSP slices, and SelectIO™ technology). These blocks are combined in different proportions to create three new FPGA families at 28 nm:

> Artix-7: Low power, low cost, high volume Spartan replacement.

> Kintex-7: Mid-range for less cost and greater performance-power than the Virtex-6

> Virtex®-7: High-end performance that challenges ASIC and ASSP markets.

Scalability is essential in a world where design reuse is one of the best ways to manage chip costs and shrinking time-to-market windows.

“In an intellectual property (IP) centric world, most customer designs come from somewhere else – a previous design, the partners or us,” notes Patrick Dorsey, Sr. Director, Product Management for Xilinx. “The capability to scale and reuse IP across multiple devices and families is critical.” Such scalability and reuse minimizes the need to re-code, re-simulate, and fix bugs when retargeting an existing design or IP block to a smaller or larger device.

In addition to a scalable architecture, the 28nm FPGAs are implemented on high-k metal gate (HKMG) technology which is optimized for lower power. This results in a 50% decrease in static power and 30% lower total power compared to FPGAs built on the alternative 28nm high-performance process, explains Mustafa Veziroglu, Vice President – Product Solutions and Management for Xilinx.

“In terms of power, most applications consume one third static, one third dynamic and one third input-output power. As we move to 28nm, we’re reducing the total power by about one half,” notes Verziroglu. This means that customers can simply run the device at the lower power level or they can use the power reduction to increase the capacity or feature set of the end-product.

Another benefit of the ever decrease power envelope of next generation FPGAs – coupled with increasing cell capacity – is that these devices may now be capable of breaking into new applications and markets currently dominated by ASICs and ASSPs. The numbers support this assertion as Xilinx claims that – in addition to low power – the 28nm FPGA families provide “2.37TMACs in DSP performance, increase capacity up to 2 million logic cells that run at up to 600MHz, and 1.9Tbps high-speed connectivity.”
In addition to offering a significant challenge to the high performance, high volume ASIC and ASSP markets, this new family of FPGAs also offers improvements into the analog component market. Specifically, the Artix 7 (unlike the equivalent low-end Spartan) can be used to replace a large number of discrete devices with a single FPGA chip. This replacement not only saves on board space and reduces overall power, but can significantly reduce the Bill of Material (BoM) costs.

Although the first 28nm FPGA devices from Xilinx won’t be available until the first quarter of next year, designer can now start using the ISE Design suites that support the 7 series family.

One Response to “Scalable Architectures Expand into FPGAs”

  1. Eric Says:

    Where is the article?

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