What do Greenpeace, CES’10 and Low Power Technology have in Common?
My quest was simply to determine the low-power requirements necessary to receive good marks in Greenpeace’s “Guide to Greener Electronics.” As with most such quests, mine led me through a thicket of related standards. But it wasn’t what I found that was surprising. What was missing turned out to be the real shocker!
At the recent CES 2010, Greenpeace announced the ecological winners and losers in its latest “Guide to Greener Electronics” report. To achieve good marks, companies are ranked by how well they meet the following goals:
– Clean up their products by eliminating hazardous substances.
– Take-back and recycle their products responsibly once they become obsolete.
– Reduce the climate impacts of their operations and product.
These goals represent a full system-wide, cradle-to-grave approach to product development, manufacturing and end-of-life disposal. Not surprisingly, few electronic companies rank successfully in all three areas.
What does this greener electronics guide mean to chip and board level designers? At first glance, not much. In fact, I had difficulty locating the actual requirements document upon which the ranking system is based. After much searching, I found the “Ranking Criteria Explained – January 2010” specification.
Hidden in the depths of this high-level spec is the portion that pertains to low-power architectural design: “Energy efficiency of new models (companies score double on this criterion).” This section, in turn, points to the government’s Energy Star standard as the basis for the ranking criteria, “rating the energy performance of three broad groups of products: external power adapters, computers (including gaming consoles) and televisions.” Several standards for each of these group categories were also cited.
Digging a bit further, I found that new models of power chargers, PCs, consoles and TVs must not only meet the Energy Star requirements, but that 30% of these new models of devices must exceed the those requirements by 50% or more in sleep and standby/no-load modes.
What do all of these requirements mean to low-power chip and board level designers? That’s the problem. Nobody seems to know how this end-product power constraint from Energy Star is allocated to the board or the chip level. I’ve talked with representatives from Power Forward Initiative (PFI), the United Power Format (UPF) and even the Power Architecture spec, but none of these organizations have talked with the higher level electronic standard groups, as represented by the U.S. government-backed Energy Star program.
Is this a real problem? In theory, once you’ve somehow achieved a successful Energy Star ranking, then all of your derivative products just need to meet the legacy power budgets. But what if you hope to develop a new product? Or if the EnergyStar criteria changes? Yes, there are tools that track requirements changes. But many of these tools have poor flow-down, that is, from an architectural level down to the board, package and chip designers.
Is it realistic to expect that these very different power-oriented organizational bodies will speak to one another? Of course not, which means that the onus for top-down power resource allocation probably will fall to the automated tool vendors in the EDA chip and board-level markets.
To their credit, the major EDA vendors, CAD companies and related design management tool suppliers have been putting more hooks into their tools to help smooth out system-level product development. Will these efforts be enough to meet the demands of an emerging ecologically driven consumer base? Time will tell.