First Impressions: Cadence’s Lip-Bu Tan
Cadence’s new CEO highlights the perils and promises facing the once dominant EDA company. Though it’s been slightly less than a month since Lip-Bu Tan was appointed president and CEO of EDA giant Cadence Design Systems, he was eager to engage the press about his plans for the company. In my first discussion with Tan, I focused on his skill sets and their impact on the future technology direction of the company.
Tan was understandably shy on details concerning specific actions he would take during the next 90 days. Instead, he emphasized that he was still working to fully understand the pain points faced by current customers, as well as dealing with the internal issues of a company that only recently lost many of its key executives .
My first question for Tan was about leadership. What did he bring to the table? His answer emphasized a strong business background. He was a venture capitalist (founder and chairman of VC elder Walden International). But he also has a technology background with an M.S. in nuclear engineering. This was encouraging, though it seems that most of his real-world experience was in the financial market. To his credit, he acknowledged that he will listen closely to the advice of his engineering brain-trust, such as: Chi-Ping Hsu, Senior VP of R&D for the Implementation Products Group, Nimish Modi, VP of R&D for the Front-End Group, and Charlie Huang, the acting CTO.
But wasn’t this the same approach used by Mike Fister, the company’s former CEO? How would Tan differ from his predecessor? In reply, Tan said that a major differentiator was in their styles of management. His will be a team approach to addressing problems. “If a team member has problem but keeps it to themselves, then that is their problem. If he/she brings it forward, then it’s our (the whole team’s) problem,” he explained. Some readers may dismiss these remarks as merely public relations jargon, but there may be more to it. Whereas Tan’s predecessor came from a large and powerful processor-specific IDM, Tan himself has the background of a venture capitalist. That suggests he will be more adept at consensus building and gathering input from many different sources – not just one portion of the semiconductor space.
He acknowledged this difference by noting that his focus has been in the broader EDA/Semiconductor market, not just at the processor world. He stated that he had good, long-term relations with more than 75% of the Cadence client base. Perhaps his biggest plus was that he didn’t have any legacy or baggage from the EDA world. This should afford him a fresh view of the challenges and possible solutions for Cadence. Or it could mean that he has a very large blind spot. Only time will tell.
Of course, knowing the company’s customer base from a financial perspective is very important. But for an EDA/Semiconductor company, you must give equal weight to an understanding of the technology. What are his plans? He said that he intends to nurture his engineering resources, including weekly review meetings. These meetings would be tied to specific customer goals, as well. This suggests a much more traditional program management approach under his tenure, with increased emphasis on meeting milestones, weighing risks and keeping to schedules.
When ask about the perceived importance of R&D at Cadence, especially in light of the rumored recent cuts to Cadence’s Berkeley labs, he replied that it was an important area that would be addressed.
He then spoke of Cadence’s existing strengths in analog/mixed-signal tools and verification. But he also emphasized the company’s strength as a system-level design company, citing early architectural estimation tools from ChipEstimate and C-to-Silicon technology through system-focused verification with Palladium and established back-end proficiency. In terms of on-going technical initiatives, he mentioned continued development in the Open Verification Methodology (OVM) and the Power Forward Initiative (including the Common Power Format or CPF with the Si2 organization). This comment about the low-power initiatives was encouraging, because some have speculated that a competing low-power format – embraced by Cadence’s rivals – has been gaining more support in the EDA/semiconductor community.
I was also glad to hear that Tan recognizes the importance of a system-level approach to chip design. Cadence seemingly exited a portion of the system-level space when it spun off SPW to CoWare in September 2004. At that time, Coware was a small company in which Cadence held an interest. Cadences renewed vigor is the system-level space at both the ESL and continued growth from the bottom-up verification level with Palladium, looks promising. I would strongly encourage Cadence to bring their package and board-level expertise into this mix, as well. This is certainly what their competitors are doing.
My final question to Tan related to events of a mere summer ago when Cadence tried to take over Mentor Graphics, based in Wilsonville, Ore. Would the EDA community see a replay of this diabolical in the future? What were Cadences M&A plans going forward? Tran didn’t answer my question about Mentor, but did say that future M&A activity is a possibility. But he quickly added that, for the near term, his focus would be on bringing Cadence back to stability in both a financial and technical sense. Judging from events of the recent past, these are indeed welcome words.