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Archive for February, 2009

Economy Exacerbates Seasonal Decline in Chip Investigations

Thursday, February 19th, 2009

Although there were slightly more architectural explorations and trade-off analysis studies performed in January’09 than in the previous month, the overall trend in such investigations continues to decline (see chart). The moving average – which serves as a predictor for trends 3-months out – also declined, but at a sharper rate. This decline is worrisome, but must be balanced with the seasonal trends for this time of year. In past cycles, the first 5 months of any given year have shown similar declines in chip investigations at the architectural level.

This data suggests that chip architects and designers are following seasonal patterns, albeit at a declining rate of new chip projects. Next time, I’ll examine our database of users for trends in which process nodes are dominant.

Chip Investigations - Jan09

Synopsys Integrates Hardware Prototyping Tools

Wednesday, February 11th, 2009

Over the past year and a half, Synopsys has been acquiring companies and parts of companies in the ASIC prototyping space. Early last year it was Synplicity, while this year it was the ChipIT portion of German-based ProDesign. What is the common thread in these acquisitions? All use FPGA-based hardware and software to prototype complex ASIC designs.

Earlier this week, Synopsys announced its expanded Confirma rapid prototyping platform. Confirma was one of the tool suites acquired from Synplicity. Below is a chart – refreshingly clean and readable – that summaries the acquired tool suits and how they (hopefully) integrate into a whole system:

Synopsys Tool Acquisition Description
HAPS Hardy – Synplicity High-performance ASIC Prototyping System
Certify Synplicity Multi-FPGA Implementation and Partitioning
Identify Pro Synplicity Debugging and Visibility Enhancement
Synplify Premier Synplicity Single-FPGA Implementation and Rapid Prototyping
CHIPit ProDesign Automated Rapid Prototyping

Integration is the key. I’m particularly interested those areas of functional overlap, such as between original Confirma suite of tools and more recently acquired ChipIT tool. Both tools provide ASIC prototyping capabilities. I discussed some of the issues in a past blog:Hardware Prototyping Market Changes Form

Synopsys’ acquisition of ChipIT would seem to strengthen its position in the system-level development market. Yet many questions remain. First and foremost is how Synopsys will integrate it most recent acquisitions of Synplicity and ProDesign’s ChipIT. For example, which of the two hardware platforms – Synplicity’s Hardi or ProDesign’s ChipIT – will it support, merge or remove? A similar question might be asked on the software side – Synplicity’s Confirma or ProDesign’s ChipIT?

One other question: How will this hardware prototyping platform eventually work with Synpopsys software (virtual) prototyping tool – from the Virtio acquisition?

First Impressions: Cadence’s Lip-Bu Tan

Friday, February 6th, 2009

Cadence’s new CEO highlights the perils and promises facing the once dominant EDA company. Though it’s been slightly less than a month since Lip-Bu Tan was appointed president and CEO of EDA giant Cadence Design Systems,  he was eager to engage the press about his plans for the company. In my first discussion with Tan, I focused on his skill sets and their impact on the future technology direction of the company.

Tan was understandably shy on details concerning specific actions he would take during the next 90 days. Instead, he emphasized that he was still working to fully understand the pain points faced by current customers, as well as dealing with the internal issues of a company that only recently lost many of its key executives .

My first question for Tan was about leadership. What did he bring to the table? His answer emphasized a strong business background. He was a venture capitalist (founder and chairman of VC elder Walden International). But he also has a technology background with an M.S. in nuclear engineering. This was encouraging, though it seems that most of his real-world experience was in the financial market. To his credit, he acknowledged that he will listen closely to the advice of his engineering brain-trust, such as: Chi-Ping Hsu, Senior VP of R&D for the Implementation Products Group, Nimish Modi, VP of R&D for the Front-End Group, and Charlie Huang, the acting CTO.

But wasn’t this the same approach used by Mike Fister, the company’s former CEO?  How would Tan differ from his predecessor? In reply, Tan said that a major differentiator was in their styles of management. His will be a team approach to addressing problems. “If a team member has problem but keeps it to themselves, then that is their problem. If he/she brings it forward, then it’s our (the whole team’s) problem,” he explained. Some readers may dismiss these remarks as merely public relations jargon, but there may be more to it. Whereas Tan’s predecessor came from a large and powerful processor-specific IDM, Tan himself has the background of a venture capitalist. That suggests he will be more adept at consensus building and gathering input from many different sources – not just one portion of the semiconductor space.

He acknowledged this difference by noting that his focus has been in the broader EDA/Semiconductor market, not just at the processor world. He stated that he had good, long-term relations with more than 75% of the Cadence client base. Perhaps his biggest plus was that he didn’t have any legacy or baggage from the EDA world. This should afford him a fresh view of the challenges and possible solutions for Cadence. Or it could mean that he has a very large blind spot. Only time will tell.

Of course, knowing the company’s customer base from a financial perspective is very important. But for an EDA/Semiconductor company, you must give equal weight to an understanding of the technology. What are his plans? He said that he intends to nurture his engineering resources, including weekly review meetings. These meetings would be tied to specific customer goals, as well. This suggests a much more traditional program management approach under his tenure, with increased emphasis on meeting milestones, weighing risks and keeping to schedules.

When ask about the perceived importance of R&D at Cadence, especially in light of the rumored recent cuts to Cadence’s Berkeley labs, he replied that it was an important area that would be addressed.

He then spoke of Cadence’s existing strengths in analog/mixed-signal tools and verification. But he also emphasized the company’s strength as a system-level design company, citing early architectural estimation tools from ChipEstimate and C-to-Silicon technology through system-focused verification with Palladium and established back-end proficiency. In terms of on-going technical initiatives, he mentioned continued development in the Open Verification Methodology (OVM) and the Power Forward Initiative (including the Common Power Format or CPF with the Si2 organization). This comment about the low-power initiatives was encouraging, because some have speculated that a competing low-power format – embraced by Cadence’s rivals – has been gaining more support in the EDA/semiconductor community.

I was also glad to hear that Tan recognizes the importance of a system-level approach to chip design. Cadence seemingly exited a portion of the system-level space when it spun off SPW to CoWare in September 2004.  At that time, Coware was a small company in which Cadence held an interest. Cadences renewed vigor is the system-level space at both the ESL and continued growth from the bottom-up verification level with Palladium, looks promising. I would strongly encourage Cadence to bring their package and board-level expertise into this mix, as well. This is certainly what their competitors are doing.

My final question to Tan related to events of a mere summer ago when Cadence tried to take over Mentor Graphics, based in Wilsonville, Ore. Would the EDA community see a replay of this diabolical in the future? What were Cadences M&A plans going forward?  Tran didn’t answer my question about Mentor, but did say that future M&A activity is a possibility. But he quickly added that, for the near term, his focus would be on bringing Cadence back to stability in both a financial and technical sense. Judging from events of the recent past, these are indeed welcome words.

Adventures at DesignCon – Twitter Logs and a Gold Stocking Woman

Tuesday, February 3rd, 2009

JohnCurious about the picture? All in good time. First, as promised, here is my summary of the inputs from all those brave participant who posted to the #DesignCon section on Twitter. Day 1 of Twitter posting were disappointing, since over half of them were press releases. Come-on, you PR and Marketing types! At least pretend that you understand what social media content is all about. Nobody is going to read a press release posted on Twitter – or Facebook, LinkedIn, Ning, or any other social space.

There where also several tweets from folks who either pointed to press releases or asked if anyone was attending a particular panel. Both struck me as hidden attempts by company reps to direct traffic to press releases or upcoming panels. File both under “lame.”

And then there was the post from harrytheASICguy. Very refreshing. He asked a question that didn’t point to a press release. Instead, Harry directed readers to an impartial online poll about which verification methodology are most designers using? OVM? VMM? You can see the results at http://tinyurl.com/bcjp8p (expand). Nice job, harry! Here’s something of real value.

Secondly, I want to share my brief adventures at DesignCon. I had only enough time to quick walk of the floor, during which time I met with Mixel, Virtutech and Altium. Mixel wanted to talk with me about an upcoming article on MIPI Camera Serial Interface with a major customer – look for that piece in an upcoming Chip Design issue.

Concerning Virtutech, my main goal was to Michel Genard, VP of Marketing. Virtutech is promoting itself as a Virtual System Design (VSD) company, as opposed to a strictly SoC focused Electronic System Design (ESD) tool vendor. This subject of system-level design, be it at the SoC, package, board or beyond, is of particular interest to me. Look for my interview with Michel in an upcoming venue.

Now, concerning the picture above with (from left to right): myself, “Bunny,” and Jim Harrison. The shot was taken at Altium’s booth. Altium was an unplanned stop for me. But once I saw it, I had to stop and ask them what was going on. Their space looked more like the inside of a hunting lodge than a trade show booth. And the tall leggy woman in gold stockings caught my eye as well. Her name was Bunny (real name was Aaron) and she was part of a marketing campaign about the dangers of overworked engineers and dating. But the real message was about their tool’s capability to lay out circuit boards in 3D, program FPGAs and perform both mechanical and electrical CAD checks. Maybe not as sexy as Bunny, but still pretty impressive. Look for my interview with Altium in an upcoming issue.

Jim Harrison, editor for Hearst’s Electronic Products, joined me for a quick shot with Bunny. Since both Jim and I are former engineers, we were by nature more interested in our electronic gadgets than in talking with an attractive woman. Right….but it makes for a good camera shot.

Finally, as I was leaving the DesignCon floor, I bumped into my old friend Georgia Marzalik from ValleyPR. She was going to a panel on “New Media/New Marketing: Using On-Line Media to Gain a Competitive Edge.” I was afraid this would be about how best to post press releases on Twitter and Facebook. But it wasn’t. Instead, it covered the growth trends in social media followed about a panel discussion from various companies with a social presence, like blogs, etc. I could only stay to listen to the first panelist – Richard Goldman, VP, Corporate Marketing – talk about social media development at Synopsys. He highlighted the importance of having blogs and of not pitching products on your blogs. Or posting press releases on Twitter. Here’s another fellow that “gets it.” Good job, Rich.

(BTW: Mentor’s CEO Wally Rhine’s keynote at DesignCon was earlier in the day and will be covered by Ann Steffora Mutschler on our (Ed Sperling and my) System-Level Design portal community.)

This ends my coverage of DesignCon and review of postings on Twitter’s DesignCon. The former is still worth attending and the later needs some work. I’ll try it again at the next big conference – maybe Multicore or ESC. Nite all.