Xilinx’s Programmable Imperative
Look for news about Xilinx’s technology roadmap in the near future. What I can say is that they are posed to reap the following benefits:
> Lower chip process nodes means lower power, better performance, smaller size. This is a no-brainer.
> Continued – perhaps even accelerated – growth into traditional ASIC markets, including standard ASIC products thanks to increase lower-node manufacturing ASIC costs; consolidation of semi industry; and niche, fast appearing consumer niche markets.
This is the first time that I’ve heard Moshi Gavrielov, Xilinx CEO, speak before an audience. Impressive, especially since he’s an engineer as well, with a background in semiconductor world and EDA.
Presentation almost done. Soon is will be time for the “cool apps” portion of the event. But here is a teaser: Air graffitti light imaging in real-time through the video camera.
BTW: Great to see that Michael Santarini – formerly with EETimes – is doing well as Editor in Chief of Xilinx’s XCell Journal.
January 27th, 2009 at 11:17 am
Do you think that eASIC is poised to reap the benefits of a struggling ASIC market rather than an FPGA vendor.
eASIC can reduce power by at least 50% over an FPGA and is much more cost effective.
Ultimately, the cost of programmability is still TOO expensive and with 70%-ish of the silicon die dedicated to just routing, an eASIC implementation would have to be a better approach?
January 27th, 2009 at 11:52 am
Hi Niall. Bit of a shameless plug for eASIC, isn’t it? Instead for pushing the company, you should push the technology.
Yes, there are good reasons to consider the use of other programmable fabrics, tho volume, IP and development tools become major considerations in addition to power consumption and cost. If you don’t that, just talk with the folks are MathLab and Ambric – now defunct.
Drop me a line if you like and we can talk about upcoming editor possibilities: jblyler@extensionmedia.com
February 8th, 2009 at 4:32 pm
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