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Archive for September, 2008

Readers Gain with New Technology Community!

Wednesday, September 24th, 2008

Ed SperlingBy the time you read these words, our new “System-Level Design� portal will have been launched. This community-focused website is sponsored by such respected companies as ARM, Mentor Graphics and Virage Logic, with others to be named shortly. It’s a website with a monthly e-Newsletter that provides content-rich dialog between readers and sponsors about the technology and trends in electronic system-level design. By content-rich, I mean valuable information conveyed in a meaningful and timely manner provided by well-known, experienced editors led by Ed Sperling, former Editor-in-Chief of Electronic News and Electronic Business. (see About Us).

The “System-Level Design� website expands beyond the Chip Design community into a more targeted technology area. Indeed, SLD is the template for future portals, providing readers with a high level of experienced editorial content. You’ll find no company press releases passing as editorial on this site.

Like the inaugural SLD portal, each future community website will use the latest Internet-based tools to provide a greater interactive experience for the user, including blogs, Ask-the-Expert forums, polls, RSS feeds, aggregation mechanisms, videos, podcasts and the like.

Chip Design continues to evolve as the industry evolves, growing beyond just EDA coverage and developing new ways to effectively deliver content.

This is an exciting time for readers and sponsors alike!

Green Power Moves Beyond the Buzz

Friday, September 12th, 2008

Earlier this week I had the pleasure of moderating a panel on “Green Power.â€? Now wait, don’t roll your eyes up and mutter “more green spin.”

Green Power panel

Not all green technology is market hype, especially when it comes to power. By power, I mean the usual suspects of lower power design and power efficient strategies. Granted, most of us have been doing low power designs for a long time, far longer than the recent “green� trend. So what new element does the green movement bring to the power design equation?

Perhaps the most important issue is the need – the imperative – to focus on true system-level design. The quest for green power is the quest for the holy grail of all electronic design (not just EDA’s ESL) a quest for a system-level understanding and subsequent implementation of a global energy solution.

Yet this broader perspective must be matched with an eye to details involving some of the most complex systems that our technical community has every faced. For example, achieving green power requires making tighter design power margins while still staying within tolerance conditions. It requires hardware and software engineers working together – really working together – at pre-architectural levels to determine the best low-power solution available for a given problem. It requires chip and board designers working together to optimize power usage for the whole system, not just their domains. It requires networking engineering working with embedded and desktop designers to achieve power efficiencies beyond those realizable today. This in term requires a feedback mechanism via existing network information infrastructures to provide data on peak usage and the general power topology for any given time and location. Finally, it requires the EDA-Semiconductor supply chain working with the broader infrastructure of their customers and of the actual consumers.

Satisfing these requirements will mean creating and encouraging open channels of communications throughout the green power ecosystem. It will mean creating initiatives, inter-operable data formats and design methodologies and tools that facilitate the development of multidiscipline, multi-vendor share of power-related data requirements and architectures. Not a trivial task.

I’ve just touched on a few of the issues confronting the “green powerâ€? challenge. Each of the panelist explored these issues and others with clarity and a pragmatic look at what can be achieve now, as well as long term. Look for video highlights of this discussion by next week.

Related Links:

Panel Participants (from left to right in picture):

  • Moderator: John Blyler, Editor-in-Chief, Chip Design and Embedded Intel Magazines
  • Cadence Design Systems: Ted Vucurevich, SVP and CTO
  • Cisco: Nikhil Jayaram, Director of Engineering, Mid-Range Router Group
  • IBM Venture Capital Group: Dr. J. Antonio Carballo, Partner, IBM Venture Capital Group
  • University of California at Berkeley: Jan Rabaey, Donald O. Pederson Distinguished Professor,
  • Silicon Valley Leadership Group: Carl Guardino, President and CEO

Nice write-up at Cadence

High Tech US Acquisitions with Foreign Assets

Thursday, September 4th, 2008

Following up on my last blog about semiconductor R&D decline in the US: Has anyone heard of CFIUS? It stands for the Committee on Foreign Investment in the United States. Lately, there has been a lot of interest in the investment community about CFISU and the high technology acquisitions of US companies with foreign assets. Sounds like the lead-in to a Dan Brown or Tom Clancy novel. Or the stuff of nightmares, if you’re worried about the decline in the US technology prowess.

For backgrounds, here’s an interesting section from the “Dept of the Treasury� CFIUS webpage:

Factors To Be Considered. The Exon-Florio provision lists the following factors that the President or his designee may consider in determining the effects of a foreign acquisition on national security. These factors are:

(1) domestic production needed for projected national defense requirements;

(2) the capability and capacity of domestic industries to meet national defense requirements, including the availability of human resources, products, technology, materials, and other supplies and services;

(3) the control of domestic industries and commercial activity by foreign citizens as it affects the capability and capacity of the U.S. to meet the requirements of national security;

(4) the potential effects of the transaction on the sales of military goods, equipment, or technology to a country that supports terrorism or proliferates missile technology or chemical and biological weapons; and

(5) the potential effects of the transaction on U.S. technological leadership in areas affecting U.S. national security.

Semiconductor R&D’s Decline in the US

Tuesday, September 2nd, 2008

I don’t have time to write about this very important topic, but my journalistic colleague from across the Willamette River in Portland, OR,  wrote a compelling story for EETimes: Bell Labs exits chip research. Here’s a portion of Colin’s report:

Bell Labs abandonment of basic research in IC materials and devices leaves the U.S. with one less semiconductor R&D center at a time when the pace on innovation is quickening and CMOS fabrication moves to advanced nodes beyond 45 nanometers.

Basic R&D investment is our hope for the future. This trend in decreased R&D doesn’t bode well for the chip industry. But more on that later.