Earlier this week I had the pleasure of moderating a panel on â€śGreen Power.â€? Now wait, don’t roll your eyes up and mutter “more green spin.”
Not all green technology is market hype, especially when it comes to power. By power, I mean the usual suspects of lower power design and power efficient strategies. Granted, most of us have been doing low power designs for a long time, far longer than the recent â€śgreenâ€? trend. So what new element does the green movement bring to the power design equation?
Perhaps the most important issue is the need â€“ the imperative â€“ to focus on true system-level design. The quest for green power is the quest for the holy grail of all electronic design (not just EDA’s ESL) a quest for a system-level understanding and subsequent implementation of a global energy solution.
Yet this broader perspective must be matched with an eye to details involving some of the most complex systems that our technical community has every faced. For example, achieving green power requires making tighter design power margins while still staying within tolerance conditions. It requires hardware and software engineers working together â€“ really working together â€“ at pre-architectural levels to determine the best low-power solution available for a given problem. It requires chip and board designers working together to optimize power usage for the whole system, not just their domains. It requires networking engineering working with embedded and desktop designers to achieve power efficiencies beyond those realizable today. This in term requires a feedback mechanism via existing network information infrastructures to provide data on peak usage and the general power topology for any given time and location. Finally, it requires the EDA-Semiconductor supply chain working with the broader infrastructure of their customers and of the actual consumers.
Satisfing these requirements will mean creating and encouraging open channels of communications throughout the green power ecosystem. It will mean creating initiatives, inter-operable data formats and design methodologies and tools that facilitate the development of multidiscipline, multi-vendor share of power-related data requirements and architectures. Not a trivial task.
I’ve just touched on a few of the issues confronting the â€śgreen powerâ€? challenge. Each of the panelist explored these issues and others with clarity and a pragmatic look at what can be achieve now, as well as long term. Look for video highlights of this discussion by next week.
Panel Participants (from left to right in picture):
- Moderator: John Blyler, Editor-in-Chief, Chip Design and Embedded Intel Magazines
- Cadence Design Systems: Ted Vucurevich, SVP and CTO
- Cisco: Nikhil Jayaram, Director of Engineering, Mid-Range Router Group
- IBM Venture Capital Group: Dr. J. Antonio Carballo, Partner, IBM Venture Capital Group
- University of California at Berkeley: Jan Rabaey, Donald O. Pederson Distinguished Professor,
- Silicon Valley Leadership Group: Carl Guardino, President and CEO
Nice write-up at Cadence