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From DAC – Three Pillars of IC Implementation

What follows over the next few days will be my quick blogs from DAC. You’ll probably find lots of typos and grammatical errors, but the content will be timely. — JB

Mentor’s press briefing (Mon, 6/9, 10AM) – JoeS talked about the integration of P&R – DFM/DFY – DFT in his Design-to-Silicon division. He gave a quick overview of each areas tool: Olympus (Sierra’s P&R acquisition from last year), Calibre and TestKompress-Yield Assist. This suite of tools address the consumerization of ICs at the lower process nodes, i.e., 45nm and below. “Consumerization,? as opposed to “corporatization,? translates to lower cost, lower power (for mobile devices), integration of multiple radios (really, multi baseband) applications.

No new, revolutionary, seamless technology was introduced at this meeting. (Thank goodness! I really dispise those marketing terms.) Rather, this briefing focused on the integration of three distinct product areas and the detail improvements realized through the hard work of such integration efforts.

Highlights from the Q&A session follow:

Question #1. Standardized language for the integrated tool suite, so big IDMs (like IBM) can levelage these tools?

Joe: Discussion for another time.

Q 2. Designers dealing with manufacturing tools?

JS: Emphasis on tool doing work, not designer doing extra work to address manufacturing variability issues.

Q3. Tapeout customers?

JS: Customers engage us when they can not get chip closure. First, we tend to get involved with optimiation – use existing tool suite. After that, clk tree syn, the router…etc. Significant players in graphcis space

4. What investments have you made. market share in this market?

JS. Joe skirted the answer to this one. I probably would have, too. — JB

5. When will these tools be fully integrated? 2 yrs from now?

JS. DRC and DFM tools are integrated now. We’ll continue to release aspects of integration over two years. addressing customers needs first.

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