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Archive for November, 2007

Why Books Will Survive

Wednesday, November 28th, 2007

But the death of paper has been predicted for decades now. Bill Powers, media critic for the National Journal, believes that paper isn’t just an old habit, but rather an advanced technology that is nearly impossible to improve upon.[Why Books Will Survive].

I certainly hope that books will survive. There is something unique, something ancient, about books. There are few pleasures as enjoyable as escaping with your favorite book to a secret place, opening the covering and reading.

Of course, most people prefer to read books that excite their imagination. Unfortunately, few technical books fire the imagination in this way. Still, technical books provide a pleasure of their own, especially those that rest near our desk, silent sentinels patiently awaiting our next inquiry. These technical books become references – close friends – that we turn to in need.

I have yet to write the first type of book, i.e., a non-technical book – tho it’s in the works. But I have co-authored two technical books, the latest of which has just been released by Elsevier. It’s not for everyone, but those folks involved in RF design may find it useful [RF Design]

RF Design

Portland Bridges are the Best!

Wednesday, November 28th, 2007

Panoramic view of Portland’s bridges made the “Picture of the Day” on Wikipedia, including the Sellwood, Ross Island, Marquam, Hawthorne, Morrision, Burnside, Steel and Fremont bridges. Very cool!

Panoramic view of Portland's bridges - 75 percent

Though my favorite Oregon bridge – next to the Astoria and Sellword bridges – is the Saint John’s Bridge. This link goes to an interesting site about the recent “St. Johns Bridge Rehabilitation Project – Oregon Department of Transportation.?

Drawing of St John's bridge

St John Bridge - 2

St John Bridge - 1

Trends in EDA-Semi Trade Shows

Tuesday, November 27th, 2007

Lou Covey has a great blog on future trends in EDA-Semi trade shows [State of the Media]. I wonder if the parallel universes of professional society conferences – like the IEEE – are suffering the same dismal fate. One hopes that engineers/managers would still attend these highly technical events, even if the events don’t generate huge revenues for their sponsors. — JB

The Dangerous Tome of Dr. Ray

Monday, November 26th, 2007

Are you ready for the long awaited sequel to “Mysteries of Reproducible Chip Design!” Can today’s chip masters really rearrange the atomic structure of matter to do their bidding? What is the previously hidden relationship between the intricate design of nano-technology chips and the fine art of master painters, like Rothko “White Center?” (see figure) What if these and other secrets fall into the wrong hands? How can the revelations of the high tech masters be protected from undesirable intentions?
Rothko - White Center

The answers to these questions lie hidden in a recently acquired manuscript of the illusive Dr. Ray. Through adventures and editorial license too terrible to mention, I’ve gained exclusive rights to publish portions of his cryptic tome. All will be revealed to those who can read between the lines – in the upcoming issue of Chip Design magazine!


A Family of Black Belts

Wednesday, November 21st, 2007

After 3 years of practice and training, my family and I – from the youngest to the oldest – passed our Tae Kwon Do Black Belt tests on Saturday, Nov 17th. What a grueling experience! But I wouldn’t have missed it for the world!

American Innovation Driven by Immigrants

Monday, November 12th, 2007

“The most striking trend is the strong growth in Chinese contributions to U.S. innovation. Since 2000, however, the contributions of Chinese scientists have leveled off, while Indian contributions showed a slight decline. This may be raising a red flag about America’s capability to innovate in the future.? – The Changing Face of American Innovation, Harvard Business School, by William R. Kerr.

This interview is well-worth reading, though I do wish the researcher would quit pitching for more research money. – JB

Past blogs on innovation issues:

> Are EDA Companies Adequately Supporting Chip Design Innovation?

> Technological Innovation Requires More than Just Money

BTW: Some of you have asked for my RSS feed. It’s listed on the right-hand side panel, as well as below:


Zero-Degrees of Freedom at 45nm

Friday, November 9th, 2007

Recently, I had the opportunity to attend Cadence’s Annual Design Chain Partners’ Event, which was held at the Corinthian Event Center – San Jose Athletic Club. I came away with the following observations:

I. Keynote by Ed Wan, senior director, Design Services Marketing at TSMC:

Ed’s talk introduced the need for close collaboration at the smaller process technologies. He used the phrase “zero degrees of freedom? between chip design and fabrication, implying a similar zero-point separation between Cadence and TSMC. I understood the marketing implication of this phrase—namely, that Cadence and TSMC are in close alignment for DFM technology. Still, I’m not sure that the phrase makes logical sense. Systems that have zero degrees of freedom yield no useful information. The system has no freedom to vary. Statistically, it would be scatter plot in which there was only one data point. Won’t there always be variations between the design and manufacturing processes? In fact, isn’t that the genesis for a DFM-DFY approach? Yes, I know I’m being pedantic. But doesn’t the term “zero degrees of freedom? imply a certain level of mathematical rigor? Chalk up these semantic differences to the inherent differences between marketing and engineering.

Ed went on to talk about the limiting factors for 45-nm design manufacturing: EDA-tool efficiency, model accuracy, and IP collaboration. He also covered some critical design-manufacturing challenges including radio frequency (RF) on chip at 65 nm. I can only imagine the parasitic problems that such a design might face. It’s a worthy topic for future editorials.

One of the fab-specific topics that Ed mentioned was the benefit—from TSMC’s perspective—of its new $10 billion “Giga Fab,? which really is three fabs in one. (Maybe it should be called a “Tri Fab??) Each Giga Fab is purported to save about half a billion dollars in building costs. The benefit of such a fab is the ability to qualify three fabs at once for volume production. Still, Ed was quick to add that TSMC will continue to reinforce its smaller and older 8-in. process fabs.

II. Breakout Sessions:

Each breakout session focused on the roadmap for a specific tool area (e.g., digital, custom ICs, and verification). These sessions were informative. For example, I learned that Cadence will never again be offering design-management tools (see Figure 1 – Photographer was Dan Peak. Thx, Dan!). Instead, the company encouraged its customers to use such tools from its Connection Members like ICmanage, Clio Soft, or Enovia (formerly Matrixone?).

Cadence Partners - Breakout

Figure 1: Steve Lewis, product marketing director for Custom IC at Cadence, discusses the roadmap during a breakout session.

III. Panel hosted by Richard Goering: “45 nm – Collaborating for Success?

Cadence Partners - Panel

Figure 2: Panel members include Ken MacWilliams, Applied Materials; Richard Brashears, Cadence; Douglas. V. Reid, Freescale; and Aiden Kelly, IBM

Richard Goering moderated a well-attended panel that looked at the need for collaboration at 45-nm chip design and manufacturing. That panel included a chip designer from Freescale, a Cadence executive representing the EDA perspective, a foundry representative from IBM, and an equipment-supplier representative from Applied Materials. In this setting, Freescale and IBM are working together under a variety of umbrella organizations—most noticeably the Common Platform Alliance. As an EDA vendor, Cadence sits comfortably in the middle—not in direct competition with IBM or Freescale (setting aside the issue of the internal EDA tools that each of these manufacturing vendors’ possess).

Cadence panel-member Richard Brashears made several observations about the changing design-manufacturing processes required at the new technology nodes. For example, he noted that there was less time to “polish up? foundry data in Cadence’s manufacturing and yield models before passing the models to the designer community. This was just one of the reasons that an open relationship with the foundries is essential.

Ken MacWilliams, the panelist from Applied Materials, talked about “double-patterning lithography? as a way of mitigating the high cost of lithography tools—some costing more than $50 million by 2009. The cool aspect of double-patterning lithography is that it allows manufacturers to use a less expensive 65-nm lithography process to print “very crisp? 32-nm lines and spaces. Very neat!

When asked about retooling EDA software for advanced manufacturing techniques, such as double patterning, Richard Brashears said that topological controls for planning and routing would probably be needed. Such controls, he noted, would adhere to traditional design rules but in a different way. And there would need to be investment in that technology as well as modeling tools.

The panelists’ predominant message was that collaboration was essential for designs at 45 nm and below. Several questions from the audience questioned the level and likely longevity of such collaboration among former competitors. Predictably, these questions received only superficial answers. But maybe I’m being too harsh in my perceptions. After all, what else would former competitors say? That while it’s painful to collaborate, there is no other path forward—especially in light of global competition and the rising cost of basic research and design? That it’s really collaborate or perish?

The event ended with closing remarks and Partner awards by Mike Fister, Cadence president and CEO, and Kevin Bushby, executive VP of Worldwide Field Operations.

All in all, a good half-day event. — JB