Quick Impressions from DAC
Jun 3 (Sun night) – First pre-DAC Sunday night event without Gartner-Dataquest reception. Replaced by EDAC executive panel and Gary Smith EDA reception. Attendance, especially at GSEDA, was high.
Event: EDAC panel, moderated by Ron Wilson and Ed Sperling (EDN). Billed as a â€śhead-to-head discussion about real-world design challenges between two industry panels – a customer panel and a vendor panel – and will reflect attendees’ input.â€?
My Perspective: Everyone was polite, as expected. Hereâ€™s the topic and summary breakdown:
1) Why is it difficult to create new architectural designs? Lots of typical answers, such as complexity, too many options to fully explore (too many degrees of freedom. Most interesting answer was from EDA tool folks in acknowledging that any given design company has â€“ at most â€“ six architectural designs. The implication was that the profit margin for such tools was too small to pursue with any great enthusiasm.
2) Why is IP so hard?
Answer: Verifying IP, especially from third parties, is very hard. Analog IP remains the most popular yet difficult to verify. IP integration is another issue â€“ may have good, verifiable IP by when integrated with other IP blocks, it just doesnâ€™t work.
3) Why is verification still a problem?
Answer: Logic verification remains the big problem. Why? Chips are so big (over 20 million gates). Test vectors grow with size. Someone (Qualcomm?) proposed less detailed verification tests and more functional tests. Reason not offered by the panel (thanks to PB): Orphan RTL – from acquisitions and mergers- is inherently unverifiable. Seems like another â€śintegrationâ€? issue to me.
4) Why is it difficult to â€śbring up silicon?
Answer: Need better models for Si. Broadcom endorsed the benefits of logic BIST as a form of risk mitigation. This option is choosen most often by experienced design.
Will try to post my impressions of Garyâ€™s event later today.