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Archive for June, 2007

EDA Media Industry at the CrossRoads

Friday, June 22nd, 2007

Have you read Lou Covey’s recent blog on the major changes occurring in the world of EDA media coverage? (http://commbasics.typepad.com/my_weblog) While I disagree with Lou’s calculation that there are only 2.25 EDA journalists left after CMP’s layoffs, I do agree with the rest of his observations (sans his bravado about “being right?).

The EDA media industry is certainly in flux. It’s not dead. In fact, it just became a wee bit more lucrative for “us? few remaining publishers. But it is becoming a low-growth market, especially with Mentor’s acquisition of Sierra (see my blog from last week). This is just one of the reasons why the big EDA equity houses – Blackstone and KKR – have explicitly pulled out of the EDA market (thanks, Pallab). Add to this the ongoing media cuts (CMP now, Penton later – IMHO) and the exodus of EDA journalist talent into other fields outside of publishing, and you have some real fundamental changes taking place.

But such changes can bring opportunities. That’s why – even though I’ll continue to cover the EDA space – I’m expanding my coverage in Chip Design magazine to include the larger world of semiconductors. Other publishing properties under my care already cover the embedded (North American and Asian) markets, vertical electronics markets and, most recently, the world of customized chip research/analysis.

Just one more observation in closing; the media buying practice that Lou cite, i.e., “not advertising and relying on press coverage for awareness,? has resulted in a big decrease in genuinely meaningful editorial product coverage. I’ve noticed that this media practice has been increasing for the last few years in both the chip and embedded publishing worlds. As a consequence, I’ve become extremely cautious in allowing any of my editors to write about specific EDA tool or embedded HW-SW products. This lack of real coverage will leave many vendors at the mercy of user group websites and various on-line discussion threads for analysis of their latest products. Not a very pleasant perspective for the vendors. But that’s what happens when you replace advertising sponsorships with press releases.

– John

And then there were three…

Monday, June 11th, 2007

Mentor now moves into the P&R world with the $90M acquisition of its partner Sierra Design, providing a competitive RTL-to-GDSII flow. Sierra brings a lithography-driven place and route tools aimed at 65 and 45nm designs. This acquisition should add further breadth to Mentor’s DFM flow. Here’s the press release: http://www.mentor.com/company/news/acquiresierradesignautomationdesigntofabflow6545nanometers.cfm

How does this change the EDA space? Instead of just two, now there are 3 significant players providing complete chip design (including P&R) flows. Some experts believe that this acquisition will increase the market’s low-growth potential, ultimately locking customers into of the three big vendor product flows. We shall see.

Cadence Buyout Coincidence

Wednesday, June 6th, 2007

“Coincidence is the word we use when we can’t see the levers and pulleys.? – E. Bull

What a coincidence?! Another Cadence rumor emerges during the DAC. This one suggests a possible buyout of Cadence by several private equity groups: Blackstone, Kohlberg Kravis Roberts (KKR), and others. While this is an interesting rumor, its timing seems far from coincidental.

So which lever do I pull to reveal the man behind the buyout curtain, Dorothy? — JB

Quick Impressions from DAC

Monday, June 4th, 2007

Jun 3 (Sun night) – First pre-DAC Sunday night event without Gartner-Dataquest reception. Replaced by EDAC executive panel and Gary Smith EDA reception. Attendance, especially at GSEDA, was high.

Event: EDAC panel, moderated by Ron Wilson and Ed Sperling (EDN). Billed as a “head-to-head discussion about real-world design challenges between two industry panels – a customer panel and a vendor panel – and will reflect attendees’ input.?

My Perspective: Everyone was polite, as expected. Here’s the topic and summary breakdown:

1) Why is it difficult to create new architectural designs? Lots of typical answers, such as complexity, too many options to fully explore (too many degrees of freedom. Most interesting answer was from EDA tool folks in acknowledging that any given design company has – at most – six architectural designs. The implication was that the profit margin for such tools was too small to pursue with any great enthusiasm.

2) Why is IP so hard?

Answer: Verifying IP, especially from third parties, is very hard. Analog IP remains the most popular yet difficult to verify. IP integration is another issue – may have good, verifiable IP by when integrated with other IP blocks, it just doesn’t work.

3) Why is verification still a problem?

Answer: Logic verification remains the big problem. Why? Chips are so big (over 20 million gates). Test vectors grow with size. Someone (Qualcomm?) proposed less detailed verification tests and more functional tests. Reason not offered by the panel (thanks to PB): Orphan RTL – from acquisitions and mergers- is inherently unverifiable. Seems like another “integration? issue to me.

4) Why is it difficult to “bring up silicon?

Answer: Need better models for Si. Broadcom endorsed the benefits of logic BIST as a form of risk mitigation. This option is choosen most often by experienced design.

Will try to post my impressions of Gary’s event later today.