JB's Circuit

At the recent AO Venture Summit,Silicon Valleyinvestors cautioned about changes to traditional investment funding models as the semiconductor market enters a cyclical downturn.

At the 2012 World Economic Forum held atDavos,Switzerland, financial leaders from around the world worry about the future of capitalism. As wealth disparity and the thread of a global recession stalks the planet, few would argue that fundamental financial changes are taking place.

One bright spot in the economic gloom is the semiconductor industry, which has experienced strong growth in recent years. But this is an industry prone to cycles that are tied closely to enterprise and consumer consumption, were the former seeks production efficiencies while the latter seeks social connectivity.

Reports suggest that this bright spot will dim slightly as the semiconductor industry enters a down cycle.  Earlier this month, speakers at the SEMI Industry Strategy Symposium (ISS) trade show predicted a chip downturn in 2013. Global foundry giant TSMC pegs the slowdown closer to 2012.

How will these changes affect the flow of investment dollars into Silicon Valley, the center of innovation for the semiconductor market? A recent panel at the AlwaysOn Venture Summit suggests that fundamental changes to the investment funding model may have a greater affect than the ongoing global financial crisis.

Venture Capital Business Outlook 2012 panel at AO Venture Summit.

What follows is a portion of a panel on the venture capital business outlook for 2012.  The host was Packy Kelly, Partner and Co-Head, US Venture Capital Practice at KPMG. Panelists included Ann Winblad, Co-founder & Managing Director at Hummer Winblad; Rob Chaplinsky, Managing Director at Bridgescale; and Paul Matteucci, General Partner at USVP.

The moderator, Packy Kelly from KPMG, started the discussion by observing that the 2011 venture capital industry was disrupted by over-funding in both the Angel and Late-Stage venture investment rounds. Lower amounts were being raised by VC firms than were being invested. He asked the panelist for their thoughts on the shape of the competitive landscape for venture capital investing in 2012.

First to answer was Ann Winblad from Hummer Winblad. She began by stating that her clients were unlimited investors that were used to longer investment cycles. To date, most venture funds try to get completed in a 10 year cycle, with a company going public after 6 years. Today things are different. She wondered if unlimited partners had the endurance to go for a longer investment cycle.

There have been many expansions and contracts of this cycle over the years. “The expansion in the 1990’s was as scary as the contractions,” said Winblad. Still, the asset class is performing well. Today, most companies don’t have an IPO exit strategy. Instead, they are looking for acquisitions. Winbald explained that she had 6 companies acquired in last year – something that hadn’t’ been anticipated. But it was good news for the venture industry. Business as usual is now over a longer period of time.

Next to comment was Paul Matteucci from USVP. He agreed that the investment cycle was taking much longer times to equity, which meant that patience and staying power are critical. Since his focus was IT, he was excited about the growth of device location technology over next 5 years. “Lots of investment will be driven by these trends, including in the medical market,” explained Matteucci.

Another growth market for location technology would be agriculture. The problem with that market was knowing when to start. You don’t want to start too soon or you’ll lose, said Matteucci, adding that the agriculture market looks like the IT industry in the 1970s.

Finishing this first round of questions was Rob Chaplinsky from Bridgescale. He felt that the current trend of investment money pouring into deals but not funds was unsustainable. A new type of venture capital approach was needed, perhaps with a greater emphasis on startup incubators. “Now, I’m not so skeptical on incubators,” said Chaplinsky. His firm had 40 companies working as incubators, most doing software programming. The average age in the incubator coders was 23-24 year olds. These people are fearless and full of energy, believing they were geniuses and with little patience for non-programmers, he observed. The challenge for VCs with these types was to develop trust early on.

On the business side of things, Chaplinsky felt that his clients see greater risk in Series A and B stages of investment. Most of them want later stage deals, further into actual product deployment. This was one sign that the VC market is going through massive changes.

Related subjects:

• EDA Inflections on Technology Innovations

Today’s announcement of Carbon’s IP Exchange portal provides evidence of the growing importance of the semiconductor IP design-manufacturing chain.

The third-party IP development chain gains additional support with today’s introduction of Carbon’s IP Exchange portal. According to Bill Neifert, Carbon’s CTO, “the portal is focused on the front-end of the design process to enable virtual platform creation and execution.”

Neifert describes the process as straight-forward: a designer logs into the portal, chooses the IP of interest and configures the block with vendor supported parameters. IP Exchange then automatically compiles a virtual model for that IP block and makes it available for download.  The model is retained on site for use by other team members or for later reconfiguration.

A few months back Synopsys introduced “TMLCentral” – another tool to aid in the front-end IP design activities. Rather than containing any information on IP blocks, the site provided transaction-level representations of IP – a valuable resource to SystemC users. According to Tom De Schutter, senior product marketing manager at Synopsys, “TLMCentral focuses solely on transaction-level modeling and virtual prototyping methodologies.”

Both of these front-end tools – Carbon’s IP Exchange and Synopsys’s TLMCentral – are complementary with the Cadence’s ChipEstimate (CE) site. Using designer selected IP, CE’s estimation tools provide trade-off analysis for a variety of backend effects, such as power consumption, die size and even cost. But the CE tools are also used early in the design process where system-wide architectural power and performance trade-offs are examined.

All of these IP portals strengthen the ability of System-on-Chip (SoC) designers to develop and integrate third-party blocks into ever complex designs. The recent introductions of front-end specific IP tools are complementary to existing architectural and back-end offerings. Together, these tool suites re-enforce the growing importance of a healthy IP ecosystem in the design of today’s semiconductor chips.

Originally posted on Chipestimate.com

Apple continues to reduce system costs through customized chip design via IP integration and software tailoring, not through traditional cost per gate.

No one doubts the intrinsic value of design reuse via third party semiconductor intellectual property (IP). Incorporating IP of known quality into a chip design allows companies to concentrate on their core design competencies while adding all the other functionality required for today’s complex System-on-Chip (SoC) integrated circuits. Large ecosystems of third party IP suppliers exist to fill this need within a royalty-based business model.

A large company can gain additional advantages over the royalty-based model through outright ownership of critical IP. Acquisition of IP allows a company to customized the IP to meet specific design needs or processes, e.g., such as low-power. Further, acquisitions give a company access to valuable technical IP in the form of engineers and process professionals. Finally, acquisitions may afford a strategic advantage to a company, allowing them to limit competition to key IP technology.

In practice, large companies follow both approaches to varying degrees. For example, ARM acquires IP companies as necessary but focuses much of its energy on building and supporting the third-party ecosystem.

Intel has recently begun in earnest to emphasize the development of its IP ecosystem – mainly consisting of companies it had acquired. (see, “Intel Challenges ARM with IP and Interconnect Strategy”)

Recent news shows that Apple follows the same approach of customizing its design chain through the IP acquisition.  Apple’s recent purchase of Anobit adds memory controller expertise to the company’s existing low-power microcontroller (PA Semi) and DSP (Integrity) portfolios.

However IP is obtained – through royalties or acquisitions – it is the game changer. “In the SoC era, system performance and development costs are not dominated by cost per gate (Moore’s Law) but rather chip design and software,” said Gus Richard, an analyst with Piper Jaffray & Co., in a report, which was obtained by SemiMD. (see, “Apple Buying Anobit as it Builds IP Portfolio,” by Mark LaPedus)

“The (Apple) A5 processor is not faster than an Intel processor, but instead it has a large number of IP blocks that execute functions with lower power and typically more quickly than a general purpose CPU. We believe that the CPU is only a portion of the SoC and has become less relevant,” he said. “This coupled with the fact that Apple’s software is written to work with one set of hardware resources significantly reduces software development cost as compared to Windows that needs to run on an infinite combination of hardware resources.”

This tight coupling between chip customization and software is replacing processor performance as the critical design driver. While this realization is nothing new, the technical reality continues to play out in a shift to subsystem rather than component IP development. Augmenting this shift to subsystem IP are the business realities of a slow global economic recovery and the very large cash reserves of many tech companies. All of which suggests that IP-based acquisitions will increase in the near future.

(First appeared in Chipestimate – InsIP ider)

Time cloaking has been demonstrated using light waves. What might that mean for particle models, as in IC applications?

Here’s a mental exercise for circuit designers. It evolves the application of a time cloak to electron particles in a digital circuit. But first, a bit of background information might help.

 Temporal cloaking allows researchers to change the perception of time. I reported on this amazing experiment last year.  (see, “Time Travel is Out: Stopping Time is In”)  

 A team of physicists at Cornell University created a time gap by briefly bending the speed of light around an event – not an object. The experiment involved changing the speeds of different light waves. The gap lasted only 50 trillionths of a second. A scaled up version of this demonstration shows an art thief walking into a museum to steal a painting without setting off laser beam alarms or even showing up on surveillance cameras. 

The time gap was demonstrated through the use of light waves. But quantum phenomena can be modeled as either waves or particles. How would a time cloak work in a particle representation?

The key to the Cornell experiment was the changing speed of different wavelengths of light. A corresponding particle representation might involve changing the speed of  electron “particles.” But electron motion is at best a statistical measurement, if one applies Heisenberg’s uncertain prediction for momentum and position.

Before exploring this challenge further, one might wonder as to the practical use of time cloaks. What could they be used for? In a circuit, the faster flow of electrons might cause an unintended output from a given set of logic functions. This assumes that the transistors could switch fast enough to operate with higher speed particles. Silicon transistors may not work, but there is an alternative.

Recent reports from IBM show that graphene switches can reach speeds of 100 gigahertz–meaning they can switch on and off 100 billion times each second, about 10 times as fast as the speediest silicon transistors. That should be fast enough for our theoretical time cloak particle experiment.

The next challenge is to create a circuit with two logic flows – one for normal speed and another for faster electrons. The faster electrons would complete their logic functions before the “normal” logic was finished. To what end, you ask? Perhaps to completely disable the rest of the circuit? This might be a problem if the circuit was part of the communication system for a fighter jet.

Of course this scenario is not that new. Many have suggested that RTL could be added to circuits just prior to fabrication in a foreign foundry to achieve the same dangerous result. (see, “Foreign Fabs and Killer Apps”) But with a time cloak, the “hidden” circuit would not be hidden at all or even added in secret. It would be there for all to see but completely undetectable except when the “time cloaked” faster electrons were activated.

Unfortunately, this scenario of a particle-based, digital time cloak is fatally flawed. An astute first year student in engineering would be able to spot the flaw in short order. Can you?

I’ll post my answer in the next blog.

A recent report by Technavio Insights confirms strong growth in IP usage and development in Asian countries. What will this mean to the future of chip design?

It has been a notable year for the semiconductor intellectual property (IP) industry. Technavio Insights, research platform of Infiniti Research, expects the global semiconductor IP market to grow at 7.75 percent year-over-year until FY2014. This growth is traced to continuous advancement in chips and electronic devices, in addition to demands in wireless, analog and optical technologies.

Total revenue for the global semiconductor IP market is driven by three key regions: theAmericas, the Europe Middle East and Africa (EMEA) and the Asia Pacific (APAC) regions. (Courtesy of TechNavio Analysis)

The birthplace of the world’s semiconductor industry – theAmericas– continues to contribute the largest share of total revenue for the global IP industry.  TechNavio reports that most of the IP vendors in the EMEA region cater to customers either in theUSor in the APAC region. This is why the EMEA region contributes only 26 percent to the overall global revenue.

Despite its relative delay into the semiconductor market, the APCA region has already outgrown the EMEA area in terms of market share. A rapidly increase in IP related activities have spurred this growth in the APAC region, as have the shifting of R&D centers from theUSandEuropeto minimize production costs.

Strong growth in the Asian IP market is one of the reasons for the introduction of major Chipestimate.com IP portals inJapanandChina. These portals will also make local Asian IP available for global consumption in the design of future chips. Such trends will lend an interesting twist to questions of IP security, theft, quality and verification. All of which will make for interesting future blogs.

(Originally posted on Chipestimate.com)

Architectural trade-offs – typically resulting in IP – made early in a design can affect a company’s market participation for years to come.

Yes – it’s a fake story. Still, it would be interesting to see the mathematics showing the reflected signal strength from 25 light years away.

Why is this story fake? As pointed out on Skeptic Friends, the first clue was the date: April 1 2009. Secondly, the story site looked like a BBC webpage the URL was hosted at rimmel.com, not BBC.

Still, I thought it was real enough to write the following post: “Set the Way-Back machine for 41 MHz, Mr. Peabody. I’m going to listen to 50 year old Dr Who reruns from 25 light years away! (Thx to Paula for pointing this out.)”

47 Year Old Television Signals Bouncing Back to Earth

“While searching deep space for extra-terrestrial signals, scientists at the Arecibo Observatory in Puerto Rico have stumbled across signals broadcast from Earth nearly half a century ago.”

It’s too bad that the story is fake AND that it cited Arecibo, an important U.S. assest that is struggling for funding. Here’s a story from my first visit to this remarkable and remote research facility: “Remote RF Telescope Bring Sci-Fi To Reality”

RF Telescope at Arecibo, Puerto Rico.

The move by Silicon Labs toward power systems integration on MCUs points to a larger trend followed by Silicon Blue and IMEC, among others.

Efficient voltage regulation is critical to the design of ultra-low powered systems.

I was reminded of this point during a recent interview with Silicon Labs. The company had just announced improvements to both its microcontroller unit (MCU) and wireless MCU for power-sensitive embedded applications. Silicon Labs claimed that their low-power technology enables 40 percent less system current draw and up to 65 percent longer battery life than competing MCU products.

The system that withdraws the least amount of energy from the battery will achieve the lowest power usage – all other conditions being equal. One way to reduce energy usage is by using highly efficient voltage conversion techniques to draw less current – both in steady state and transient or “spiking” scenarios. Improved energy efficiency was a key part of the recent Silicon Labs announcement. But it also lead to an interesting side discussion about energy scavenging systems.

One way to make battery power last longer is through power efficiency. Another is by restoring energy to the battery, e.g., with an alternative energy system. I asked Silicon Labs if their improved MCUs platforms would interface with energy scavengers.

Keith Odland, the company’s  MCU marketing manager, explained that the challenge with interfacing to energy scavenging devices lies with the power inputs. As an example, he cited the use of piezoelectric elements – common in scavenging systems. Even though these devices output micojoules of power, they can still create large voltage spikes in the tens to hundreds order of magnitude.

The voltage regulation techniques that the company has incorporated into their MCUs to improve energy efficiency will also help prepare them to handle future energy scavenging systems. “All of these improvements will … accommodate non-traditional energy sources – things like switching regulators that are boost converters; switching regulators that are buck converters; wide operating ranges; linear regulating systems and temporary energy storage devices.”

Odland did caution that, while intriguing, many energy scavenging devices don’t yet have the economic drivers to push them beyond what is available in most battery platforms. “The exceptions are devices embedded into bridge suspensions and things on top of radio towers that have high servicing costs,” he said. Today, it is still cheaper to replace a $0.15 battery then design a new energy scavenging system.

He noted that the market is beginning to see more creative energy scavenging systems come into main stream, e.g., tire pressure monitoring systems. (see, “Power Bits: Smarter Tires, After CMOS”)

Another alternative power source that is gaining momentum is solar. Here, too, ultra low power is critical to success as was recently demonstrated by the Citizen Watch’s selection of Silicon Blue’s ultra-low power FPGA IP into their solar-powered, Eco-Drive Satellite Wave watch. Citizen claims that this is the world’s first light-powered GPS-synchronized watch.

Regardless of when alternative energy sources like solar and scavengers go main stream, having high efficiency energy conversion capabilities integrated into the same chip as the processor will help designers both now and in the future.

Regardless of system-design approach, painful tradeoffs are still needed–usually during integration.

Earlier this month, Steve Leibson shared his “prognostications from the ICCAD panel” concerning the shape of things to come for the EDA and chip design industry.

The part of this blog that caught my attention was the comments made by Patrick Groeneveld, Magma’s Chief Technologist and the General Chair for DAC 2012. Groeneveld acknowledged two paths to handling chip design complexity: partitioning and reuse. But he believed that both of the paths were evil since they introduce inefficiencies in the overall design.

Leibson disagreed; pointing out that the divide-and-conquer method was a tried and ture approach, dating back to theRoman Empire. “…it’s an approach that seems to have withstood the test of time. However, a divide-and-conquer strategy does indeed lead to suboptimal design in terms of efficient resource use. I just don’t know of any engineering discipline that avoids such inefficiencies when tackling projects of comparable complexity. Is it hubris to think that electrical engineering and chip design are somehow different?

Both Groeneveld and Leibson offer classic arguments to the age-old problem of dealing with complexity. There are no new solutions to this dilemma, only a re-shifting of unpleasant trade-offs. In a broader sense, this re-shifting can be thought of as maintaining the “Conservation of Design Pain.” I use the word “design” for brevity and rhythm. To be correct, I should have used “development” since the pain is spread across the full system/product life-cycle effects, from design through manufacturing.

This law of “pain” acknowledges the shifting of difficult decisions to different parts of the development cycle, depending upon the methodology. For example, both partitioning and reuse are useful techniques that overcome certain design complexities by increasing the design pain in other areas, namely, in integration.

Centuries of systems engineering confirm that most systems work best when they have low coupling and high cohesion between subsystems. This is a golden rule in the partitioning between (and within) hardware and software systems. Reuse follows the same rule, with the added advantage of functionally verified blocks of design.

By reducing complexity, both partitioning and reuse simplify the work of design engineers. For example, by utilizing code or hardware reuse, engineers don’t have to design everything, which affords them more time to concentrate on designing in there area of  expertise. This leads to greater specialization, which is can be good.

But it also leads to a greater need for reintegration and often increases the complexity of interfaces. This effectively shifts the “pain” from the module to the interface subsystem.

Shifting pain from one part of the development cycle is the result of dealing with complexity. If recent trends are any indication, then the integration engineers are in for a world of hurt.

Gamification is moving from social media networks to technical sites for both motivational and generational reasons. Engineers will have to play to win.

Let’s play a little game. First, start with a noun. Let’s choose the noun, “game.” Now, add the suffix “ification” to the noun. The result is a new word (no longer a noun) that seems to add something more to the original meaning of the word. Wasn’t that fun? No? Well, it was at least engaging.

Why should semiconductor intellectual property (IP) professionals care about the growth of gamification systems? The reason is that their careers may depend upon it. I’ll explain what I mean shortly, but first I need to briefly cover this emerging field, starting with its use in popular social media applications.

Gamification is the act of changing a traditional non-game activity into a game. Wikipedia offers this definition: “Gamification is the use of game design techniques and mechanics to solve problems and engage audiences.” Note the last phrase, i.e., “engage audiences.” Gamification is not about making every activity or process fun, but rather making these experiences engaging and motivating.

What are some examples of a good gamification experience? Here is a list of the recent applications:

• Foursquare: A location-based mobile platform that makes cities easier to use and more interesting to explore. Users check-in via a smarphone application of SMS, sharing their location with friends while collecting points and badges. The company claims a membership of over 10 million people worldwide.
• Farmville: A simulation social network game that involves farm management activities like plowing, planting, growing, etc. Players invite friends to be neighbors, who may then share gifts and supplies with one another. The Facebook site claims 30 million users monthly.
• EpicWin: A solo play scenario with this twist – players create personalized role-playing game (PRG) characters based on their real life to-do list. From the site: “Make being organized as much fun as gaming with EpicWin the to-do list app with an RPG setting.”

Before you shrug off gamification as a time consuming activity of questionable real-world value, consider one more example. Stack Overflow is a very popular programming question-and-answer site. It is a free site (no registration) where users ask and answer questions, gaining “karma and winning valuable flair that will appear next to (their) name.”

Mention gamification to many hardware engineers and they will envision their last massively multiplayer online (MMO) game adventure at a LANfest (or equivalent) competition.

Is there a similar site for hardware engineers? Not that I know of, but there should be. Why not have a site called “Black Box I/O,” where hardware IP designers and verification engineers could go to ask questions and get answers about integrating common types of IP?

 Black Box I/O – The place where semiconductor IP developers engage and earn valuable integration tips. Earn the respect of your core colleague with distinctive SoC badges, Facebook “Likes” and even frequent flier miles.

Some might argue against the need for such a gamification approach, noting that semiconductor IP suppliers already provide specific interface information and models. Past columns have addressed some of the shortcomings with these models, (see, “IP Characterization Moves from The Backroom,”)

If reuse is to grow as quickly as most analyst predict, then the need to integrate disparate blocks of IP will also grow. Some of reuse might even come from providers of open source cores, like OpenCores.org  Both of these trends will increase the need for web sites where developers can post questions and get answers. Gamification techniques would provide the engagement and motivation to keep such a Q&A site going with a minimum of outside support.

Before too long, some smart and enterprising professional inSilicon Valleywill apply the techniques of gamification to IP design.

I can hear my hardware colleagues now: “That’s crazy. Our designs are too complex. Besides, we are a(n) BLANK house – (ARM, Intel, etc.). We use proprietary interfaces like BLANK (AMBA, ISOF, etc) to interconnect most of our cores. If we have questions, we ask the IP supplier directly.”

It might well turn out that the first successful semiconductor IP gamification site will be launched by one of the large ecosystem leaders, like ARM, Intel or Chipestimate – rather than from a single person or small team with VC backing. The large players could easily augment their touted user group communities with gamification techniques. It will happen.

When it does, the next generation of engineers will be ready. They are already being gamified. The proliferation of the video games, social media and engagement activities on the Internet means that the next generation of engineers and managers will be easily affected by gamification techniques. Today’s kids are easily bored if not engaged. Gamification will be one way to increase productivity and pass on learning, while dealing with the increase need for stimulation and shrinking attention spans of future technologists.

(BTW: For an insightful discussion as to the dangers of such an activity – especially to non-technical business and marketing types – check out this article: “Gamification… or is that exploitification?”)

Gabe Zichermann on gamification.

Special Event Notice: Gabe Zichermann, CEO of Gamification, Inc., and author of “Gamification by Design” (O’Reilly, 2011), will speak this Thursday ( 11/17/11) at the Arlene Schnitzer Concert Hall as part of the ISEPP lecture series.

(First published on Chipestimate.com under “IP Insider.”)