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Is Hardware Really That Much Different From Software

November 30th, 2014

When can hardware be considered as software? Are software flows less complex? Why are hardware tools less up-to-date? Experts from ARM, Jama Software and Imec propose the answers.

By John Blyler, Editorial Director

HiResThe Internet-of-Things will bring hardware and software designers into closer collaboration than every before. Understanding the working differences between both technical domains in terms of design approaches and terminology will be the first step in harmonizing the relationships between these occasionally contentious camps. What are the these differences in hardware and software design approaches? To answer that question, I talked with the technical experts including Harmke De Groot, Program Director Ultra-Low Power Technologies at Imec; Jonathan Austin, Senior Software Engineer at ARM; and Eric Nguyen, Director of Business Intelligence at Jama Software; . What follows is a portion of their responses. — JB

Blyler: The Internet-of-Things (IoT) will bring a greater mix of both HW and SW IP issues to systems developers. But hardware and software developers use the same words to mean different things. What do you see as the real differences between hardware and software IP?

De Groot: Hardware IP, and with that I include very low level software, is usually optimized for different categories of devices, i.e. devices on small batteries or harvesters, medium size batteries like mobile phones and laptops and connected to the mains. Software IP, especially for the higher layers, i.e. middleware and up can easier be developed to scale and fit many platforms with less adaptation. However practice learns that scaling for IoT of software also has its limitations, for very resource limited devices special measures have to be taken. For example direct retrieval of data from the cloud and combining this with local sensor data by a very small sensor node is a partly unsolved challenge today. For mobiles, laptops and more performing devices there are reasonable solutions (though also not perfect yet) to retrieve cloud data and combine this with the sensor information from the device in real-time. For sensoric devices with more resource constraints working on smaller batteries this is not so easy, especially not with heterogeneous networking challenges. Sending data to the cloud (potentially via a gateway device as a mobile phone, laptop or special router) seems to work reasonably, but retrieving the right data from the cloud to combine with the sensor data of the small sensor node itself for real-time use is a challenge to be solved.

Austin: Personally, I see two significant differences between the real differences between hardware and software design and tools:

  1. How hard it is to change something when you get it wrong? It is ‘really hard’ for hardware, and somewhere on spectrum from ‘really hard’ to ‘completely trivial’ in software.
  2. The tradeoffs around adding abstraction to help deal with complexity. Software is typically able to ‘absorb’ more of this overhead than hardware. Also, in software it is far easier to only optimize the fast path. In fact, there usually isn’t as much impact to an unoptimised slow path (as would be the case in hardware.)
  3. There are differences in the tool sets. This was an interesting part of an ongoing debate with my colleagues. We couldn’t quite get to the bottom of why it is so common for hardware projects to stick with really old tools for so long. Some possible ideas included:
  • The (hardware) flow is more complex, so getting something that works well takes longer, requires more investment and results in a higher cost to switch tools.
  • There’s far less competition in the hardware design space so things aren’t pushed as much. This point is compounded by the one above, but the two sort of play together to slow things down.
  • The tools are hardware to write and more complex to use. This was contentious, but I think on balance, some of the simplicity and elegance available in software comes because people solve some really touch physical issues in the hardware tools.

So, this sort of thinking led me to an analogy of considering hardware to be very low level software. We could have a similar debate about javascript productivity versus C – and I think the arguments on either side would like quite similar to the software versus hardware arguments.

Finally on tools, I think it might be significant that the tools for building hardware are *software* tools, and the tools for building software are *also* software tools. If a tool for building software (say a compiler) is broken, or poor in some way, the software engineer feels able to fix it. If a hardware tool is broken in some way, the hardware engineer is less likely to feel like it is easy to just switch tasks quickly and fix it. So that is I guess to say, software tools are build for software engineers by software engineers, and hardware tools are built by software engineers to be sold to companies, to be given to hardware engineers!

Nguyen: One of the historical differences relates to the way integrated system companies organized their teams. As marketing requirements came in, the systems engineers in the hardware group would lay out the overall design. Most of the required features and functionality were very electrical and mechanical in nature, where software was limited to drivers and firmware for embedded electronics.

Today, software plays a much bigger role than hardware and many large companies have difficulties incorporating this new mindset. Software teams move at a much faster pace than hardware. On the other hand, software teams have a hard time integrating with the tool sets, processes and methodologies of the hardware teams. From a management perspective, the “hardware first” paradigm has been flipped. Now it is a more of software driven design process where the main question is how much of the initial requirements can be accomplished in software. The hardware is then seen as the enabler for the overall (end-user) experience. For example, consider Google’s Nest Thermostat. It was designed as a software experience with the hardware brought in later.

Blyler: Thank you.

Review of Jama, ARM Techcon and TSMC OIP Shows

November 14th, 2014

October issues of the “Silicon Valley High-Tech Traveler Log” – with Sean O’Kane and John Blyler

Three events from TSMC, ARM and JAMA Software highlight the breadth and depth of IP development that (hopefully) results in manual-less consumer apps.

A few week’s ago, I attended three shows -  Jama’s Software Product Delivery SummitTSMC’s Open Innovation Platform (OIP) and ARM’s Techcon. While each event was markedly different there was an unintentional common thread, i.e., all three dealt with the interplay between hardware and software IP systems – albeit on different levels of the supply chain.

Each of these shows characterized that interplay in different ways. For TSMC, it was a focus on deep semiconductor manufacturing-related IP. Conversely, Jama Software dealt with product delivery issues for which embedded hardware and application software played a major role. Embedded software on boards running the company’s flagship processors and ecosystem IP hardware peripherals was the focus at the ARM Techcon. Why are these various instantiations of IP important?

Read the rest of the story at: IP-Based Technology without Manuals?







Soft (Hardware) and Software IP Rule the IoT

September 2nd, 2014

By John Blyler, JB Systems

Both soft (hardware) and software IP should dominate in the IoT market. But for which segments will that growth occur? See what the experts from IPExtreme, Atmel, GarySmithEDA, Semico Research and Jama Software are thinking.

The Internet-of-Things will significantly increase the diversity and amount of semiconductor IP. But what will be the specific trends among the hardware and software IP communities? Experts from both domains shared there perceptions including,  Warren Savage, President and CEO of IPExtreme; Patrick Sullivan, VP of Marketing, MCU Business Unit for Atmel; Gary Smith, Founder and Chief Analyst for Gary Smith EDA; Richard Wawrzyniak, Senior Market Analyst for ASIC & SoC at Semico Research, and; Eric Nguyen, Director of Business Intelligence at Jama Software. What follows is a portion of their responses. — JB

Blyler: Do you expect an accelerated growth of both hardware and software IP (maybe subsystem IP) due to the growth of the IoT? What are the growth trends for electronic hardware and software IP?

Savage: I don’t think that there is anything special about the Internet-of-Things (IoT) from an intellectual property (IP) perspective.   The prospect of IoT simply means there is going to be a lot more silicon in the world as we start attaching networking to things that previously were not connected. As a natural evolution of the semiconductor market, hardware and software IP is going to keep growing and will outpace everything else for the foreseeable future. Subsystems are a natural artifact of that maturing as well as customers wanting to do more and more with less people, outsourcing whole functions of chips to be delivered from their IP supplier who is likely an expert in that subject matter.

Sullivan: The largest growth will be in software IP for hardware IPs that already exists in order to connect devices to the Internet. Developers that are not familiar with wireless applications will find themselves making connected devices, and for suppliers to have context aware stacks and other IP tailored for the different IoT usage models will be crucial. i.e.; just having a ZigBee stack is not sufficient. You need a version for healthcare, a version for lighting, and so on.

Security is also going to be an important factor for both securing communication between IoT devices and the cloud (SSL/TLS technologies), and also to authenticate that firmware images running on connected devices have not been tampered with. Addressing these needs may require additional software development of IoT devices, and potentially specialized hardware components as well.

On the hardware side, the main focus will continue to be power consumption reduction as well as range and quality improvements.

Smith: Yes, growth in hardware and software IP will increase with the IoT expansion. However, the IoT market comprise multiple segments. To get accurate growth figures you would need to explore them all (see Table).

Table: Markets for the Internet-of-Things. (Courtesy of

Wawrzyniak: I do expect some acceleration of revenues derived from IP going into IoT applications. At this point it is hard to determine just how much acceleration there will be since we are just at the very beginning of this trend. It also will depend upon which types of IP are chosen as the ones most favored by SoC designers. For example, if designers select of one of the wireless IP types as the preeminent solution, then this might be more expensive (generate more IP revenue over time) than say ZigBee.

Given the sheer volume of IoT applications and silicon being projected, it is possible that once a specific process geometry is decided on as the optimum type to use, the IP characterized for that geometry might actually be less expensive than the same IP at another geometry. Volume will drive cost in this case. All these factors will go into figuring out how much additional IP revenue will be generated. I would say a safe estimate today would be on the order of 10%.Wawrzyniak: I do expect some acceleration of revenues derived from IP going into IoT applications. At this point it is hard to determine just how much acceleration there will be since we are just at the very beginning of this trend. It also will depend upon which types of IP are chosen as the ones most favored by SoC designers. For example, if designers select of one of the wireless IP types as the preeminent solution, then this might be more expensive (generate more IP revenue over time) than say ZigBee.

I also think it’s likely that IP Subsystems will be created for IoT applications. Again, this depends on how complex the silicon solution will need to be. If we are talking lightbulbs, then it is hard to imagine that an IP Subsystem will be needed. On the other hand, a relatively complex chip might require an IP subsystem, e.g., a Sensor Fusion Hub subsystem. Sensors will certainly be everywhere in the IoT, so why not create a subsystem that deals with this part of the solution and ties it all together from the designer

Hard IP will probably be more expensive than Soft IP. I would say that Soft IP will be used more in these types of SoCs. I would estimate that it could be as high as a 70 – 30 split in favor of Soft IP.

Nguyen: Absolutely, the growth of IoT will not only open new markets such as wearable technologies and home automation but will also cause disruption in existing due to software based services being delivered through connected devices. Technology products are evolving from electro-mechanical based IP competitive differentiation to customer experience differentiation powered by software applications running on optimized hardware.

The trends in hardware and software IP are accelerating the rate of innovation for customer facing products, which in turn will have a direct impact throughout the supply chain. Software producers must mange the interdependencies not only across their product lines but also across the various technologies they’ll be deployed on (i.e. iOS, Android, Web, integrated into 3rd party technology) or various subsystems. The connected aspect of these technologies allows vendors to continually update the offerings and therefore evolve the customer experience throughout the life of the physical technology.

The performance demands of continuously evolving software heavy products is also driving accelerated innovations throughout the supply chain, specifically hardware components such as Systems on Chip, Systems in a Package, sensor technology, and battery/power management.

Final product producers are also accelerating release cycles and therefore driving the need to more easily integrate sub-components. This demand is driving the demand for Systems in a Package (SiP) technologies, which incorporate the chips, drivers, and software within a physical sub-component package that can easily integrated into the overall system. Semiconductor companies must now coordinate the growing complexity of silicon, software, and documentation development while accelerating their ability to incorporate market feedback into product roadmaps, R&D, and ultimate manufacturing and delivery to customers; all the while ensuring they can meet per unit cost targets.

Blyler: Thank you.

Weekly Chip-Science Highlights – Aug. 15th

August 15th, 2014

By John Blyler

More on Moore’s Law; Thought-Controlled Cameras; Neurons on Chip; IP Bag; Quantum Dots and blogs.

Here’s a mixed of semiconductor-related articles and blogs that caught my attention this week:

  • Can our computers continue to get smaller and more powerful? – Have we reached the limits to computation? In a review article in this week’s issue of the journal Nature, Igor Markov of the University of Michigan reviews limiting factors in the development of computing systems to help determine what is achievable, identifying “loose” limits and viable opportunities for advancements through the use of emerging technologies. His research for this project was funded in part by the National Science Foundation (NSF).
  • Thought-Controlled Camera Confirms IoT Trends – Software start-ups will dominate growth in the Internet-of-Things (IoT) as demonstrated by MindRDR’s application that combines Google Glass and Neurosky biosensor hardware.
  • Brain-inspired chip fits 1m ‘neurons’ on postage stamp – Scientists have produced a new computer chip that mimics the organization of the brain, and squeezed in one million computational units called “neurons”. They describe it as a supercomputer the size of a postage stamp. Each neuron on the chip connects to 256 others, and together they can pick out the key features in a visual scene in real time, using very little power.

Figure: TrueNorth is the first single, self-contained chip to achieve 256 million individually programmable synapses on chip which is a new paradigm. (TrueNorth Core Array, Courtesy of IBM)

  • (Potato) Chip Bags IP – The latest research from MIT, Microsoft and Adobe on recovering speech from the vibrations of ordinary objects confirms the growing importance of software IP.
  • With sharp focus, quantum dot makers scale up to meet demand – This Reuters article discusses the huge growth in the demand quantum dots, the semiconductor crystals that use less power and are cheaper than organic LEDs.


Industry Blogs:

  • Kathryn Kranen discusses Jasper, formal verification and the Cadence Acquisition.
  • Mentor’s Colin Walls shares his love of writing, especially embedded software articles about assembly language to software IP.
  • Another interesting blog from Mentor. This time, Christopher Hallinan explores hardware and software complexity via th Yocto Project.
  • Summer is a time for big trips. Synopsys’s Tom d Schutter recently shared an adventure with his family through the westernUS states. That trip sparked comparisons with the task of staring a virtual prototyping project. Finding similarities between function trace information and the unexpected buffalo crossings atYellowstoneNational Park is not an easy task, but Tom pulls it off.
  • Satellite Crowdfunding, Then and Now – Did you know that the first satellite sent up by theUnited Stateswas originally planned to be crowdfunded? Did you also know that the newest amateur satellite sent up in the third quarter of next year will be crowdfunded as well? by Hamilton Carter


Our Day at DAC – Day 2 (Tuesday)

June 2nd, 2014

Here are the brief observations on noteworthy presentations, cool demonstrations and hall-way chats from the Chip Design editorial staff covering DAC 2014.

Report from Gabe Moretti:

EDA is Alive and Ready for Another Year of Growth

The second day of DAC was a very busy one for me. I met with Dassault Systeme that showed me an impressive approach to EDA based on project management system that provides different views of the state of the project depending on the viewer position in the project. For example, project manager, individual engineer, verification engineer, and so on. I met with Verific and Invionics two different companies that have found a symbiotic way to expand the market they serve without competing with each other.
Synopsys described their approach to the automotive market. The presentation described almost perfectly my 2014 Lincoln MKZ hybrid. It is impressive to see technology becoming reality as I write.
Carbon is growing, revenues were up 46% last year and diversifying. They were not quite ready for a big announcement at DAC but I was told it would be made before the end of this month.

Much work is going on in formal verification embolden by Cadence acquisition of Jasper Design.
More meetings are scheduled for tomorrow and I promise a final impression of what DAC meant for me.


Report from Hamilton Carter:

DAC Meanderings, 51st DAC (6/3)


The day started early with the Accelera breakfast.  The food was excellent.  There were “Fluffy scrambled eggs”, bacon, sausage and a variety of pastries. For the first half hour or so folks straggled in, slowly orienting themselves after the first night of DAC parties. The proceedings kicked off with the handling of a few business issues.  Shishpal Rawat, the current Accelera chairman outlined the achievement of the prior year and the goals and schedule of the ensuing one. The last order of business was the presentation of the Accelera Leadership Award for 2014 to Yatin Trivedi, (pictured).

A few moments later, Doulos’ John Ainsley, ever-spry, bounded onto the stage to introduce the members of his UVM roundtable.

John played devil’s advocate to keep the panel lively. He first asked what the members’ general feelings on System Verilog were. When all the panelists agreed that they were generally happy, John then prodded each of them to find out how happy they were, why, and what challenges they were still having. The general consensus seemed to be as follows:

  • Asking designers to adopt object oriented class-based solution was a hard sale.
  • Finally having a uniform standard offered by all the vendors was very, very nice.
  • There were hiccups and burps along the way as internal libraries needed to be converted to the new standard and IP vendors tended not to have adopted the standard yet.

From the Accelera breakfast a brief walk brought me to the first time exhibitors’ interviews.

Silicon Cloud
Marc Edwards, presenting for Silicon Cloud, described his vision of moving the engineering flow into the cloud.  Allowing startups and others to avert the expense of large hardware box purchases.  Silicon Cloud offers a solution that moves all design tools, licenses, and IP into a server space they maintain and monitor.  The places 1000s of virtual machines at the disposal of design engineers who access the cloud via Chrome books that have been walled from the rest of the internet.  All transactions that touch the design, IP, or tools are recorded.  In addition to providing valuable information on the process flow and the usage of tools and IP, Silicon Cloud also watches for nefarious and/or non-conformal behavior with regards to the management of IP.

Larry Lapides presented Imperas’ services and product portfolio.  The company is focusing on software verification in the embedded realm.  Their portfolio of over 140 open access processor and peripheral models allows their customers to bring up their software ahead of design completion.  The models run at millions of cycles per seconds allowing very comprehensive software scenarios.  Automotive and medical embedded applications, where software failure is not an option, are adopting Imperas’ testing and system reliability tools and methodology.

Harnhua Ng presented Plunify’s FPGA-build optimizing solution.  Their tool watches FPGA builds. which can take days to not converge, and provides early warning that non-convergence is imminent.  The tool also points out the likely causes of the non-convergence within the design so that a successful build can be achieved next time.  In addition to its dynamic build-watching features, the tool also has a static facility that scans the design-to-be-built and warns of known issues before the build begins.

Jason Png, OPTIC2connect’s founder and CEO, gave a brief presentation of his company’s optical interconnect prototyping services.  He said they don’t intend to replace design engineers, just make their jobs much simpler.   OPTIC2connect has helped their customers move their prototyping cycles for optically enabled bus infrastructures from six months to three weeks.

Synopsys is back in the Formal Verification Market
From a round of interviews with the new guard of EDA, I proceeded to an interview with one of the older names in EDA, Synopsys.  Synopsys is announcing their new entry into the formal/static verification market at this year’s DAC.  The all new tool introduces capabilities for formal verification, clock domain crossing, and low power static checking with other features on the way soon.  The tool can load in chip level, fully-flattened RTL designs to facilitate proper low power and interconnect checking.  It also sports simplified and compressed error output.  Gone are the days of day long design checks followed by searching through gigabytes of data for the error that matters.  The tool bundles errors up to their root cause which is reported along with the count of other errors that are attributed to the root.  For those that sill want to get into the gory details for themselves, an API is provided for teasing every last bit of available data out of a formal/static verification run.

Jasper’s food truck party
Jasper brought three busloads of engineers and semiconductor industry aficionados to Treasure Island earlier today to partake of the delicious wares of five different food trucks.

Entertainment was provided by Rat-Pack styled musicians, a magician, a juggler, and a lawyer turned professional bubble maker.

A great time was had by all, and CEO Jasper CEO Kathryn Kranen, thanked the Jasper team for their excellent work.

Our Day at DAC – Day 1 (Monday)

June 2nd, 2014

Here are the brief observations on noteworthy presentations, cool demonstrations and hall-way chats from the editorial staff covering “Day 1″ at DAC 2014 – John Blyler, Gabe Moretti and Hamilton Carter.


DAC Report from Hamilton Carter:

Puuurrrple, so much purple!  The stage at the packed Synopsys, Samsung, ARM briefing this morning was backed by ceiling to floor Synopsys-purple curtains.  The Samsung vision video played on the two large screens on either side of the stage.  To steal a phrase from “Love Actually”, Samsung’s vision is that “touch-screens are… everywhere” .  Among the envisioned apps were a touch screen floor for your kids’ room, complete with planetarium app; a touchscreen window for your Town-Car so you can adjust the thermostat in the car as your driver taxis you to your destintion; and finally a touchscreen gadget for the kitchen that when laid flat weighs the food and registers the number of calories in the amount you’ve sliced off on its cutting board tough screen, displays the recipe you’re using when upright, and finally, get ready for it… checks the ‘safety’ of your food displaying an all clear icon complete with a rad safe emblem.  Apparently the future isn’t completely utopian!

Phil Dworsky, director of strategic alliances, for Synopsys introduced the three featured speakers, Kelvin Low, of Samsung, Glenn Dukes of Synopsys, and Rob Aitken from ARM, and things got under way.  The key impetus of the presentation was that the Samsung/Synopsys/ARM collaboration on 14 nm 3D finfet technology is ready to go.  The technology has been rolled out on 30 test chips and 5 customer chips that are going into production.

Most of the emphasis was on the 14 nm process nodes, but the speakers were also quick to point out that the 28 nm node wasn’t going away anytime soon  With its single patterning, and reduced power consumption, it’s seen as a perfect fit for mobile devices that don’t need the cutting edge of performance yet.

Interesting bits:

  • It was nice to visit with Sanjay Gupta, previously of IBM Austin, who is now at Qualcomm, San Diego.
  • While smart phones have been outshipping PCs for a while, tablets are now predicted to outship PCs starting in 2015.
  • Bryan Bailey of verification fame was one of the raffle winners.  He’s now a part of the IoT!
  • IoT predictions are still in the Carl Sagan range, there will be ‘billions and billions’.
  • Samsung GLOBALFOUNDRIES has a fab, Fab8, in Saratoga, NY.
  • Last year’s buzzword was ‘metric driven’, this year’s is ‘ecosystem’ so far.  The vision being plugged is collaborations of companies and/or tools that work as a ‘seamless, [goes without saying], ecosystem’.

Catching up with Amiq

I got to catch up with Christian from Amiq this morning.  Since they’re planted squarely in the IDE business, Amiq gets the fun job of working directly with silicon design and verification engineers.  There products on display this year include their Eclipse based work environment, with support for e, and SystemVerilog built in, their verification-code-centric linting tool Verissimo, and their documentation generation system Specador.

IC Manage

I’m always drawn in by a good ‘wrap a measurable, or at least documentable flow around your design process story’, so I dropped by the IC Manage booth this morning.

Their product encapsulates many of the vagaries of the IC development flow into a configuration management tool.  The backbone of the tool can be customized to the customer’s specific flow via scripts, and it provides a real-time updated HTML based view of what engineers are up to as project development unfolds.


DAC Report from Gabe Moretti:

Power Management and IP

Moscone South is all about IP and low power.  This is the 51st DAC and my 34th.  Time flies.  The most intimidating thing is that the Apple Developers Forum is going on at the same time, and they have TV trucks and live interview on the street.  We of course do not.  It was nice to hear Antun Domic as one of the two keynote speakers this morning  His discussion on how the latest EDA tools are used to produce designs fabricated with processes as old as 180 nanometers was refreshing.  In general people equate the latest EDA tools with the latest semiconductor process.  Yet one needs to manage power even at 180 nanometers.

Chip Estimate runs a series of talks from IP developers in its booth.  I listened to Peter Mc Guiness of Imagination Technologies talk about advances in image processing.  it was interesting to hear him talk about lane departure warning as an automotive feature employing such technology.  Now I know how it works in one of my cars.  On the other hand to hear how the retail industry is planning to use facial recognition to choose for me what I should be interested in purchasing is not so reassuring.  But, on the other hand, its use in robotics applications is fashinating.


DAC Report from John Blyler:

I. IP Panel: The founders for several successful private IP companies shared their experiences with an audience of near 50 attendees. The panelist included CAST, IPExtreme, Methods2Business, and Recore Systems. The main takeaways were that starting an IP company takes passion and a plan.  But neither will work if you don’t have some product to offer and a few key relationships in the industry. (Warren said you need 3 key customers to start.) I’ll write more about this panel later. Here’s a link to a pre-DAC position statements from the panelist.

II. NI and Cadence – The Best of Both Worlds

George Zafiropoulos, VP, Solutions Marketing at National Instruments (NI)-AWR, has brought his many years of chip design and verification experience from the EDA industry to NI. He spoke at the DAC Cadence Theater about post- and pre-silicon verification being the best of both worlds. Those worlds consist of NI, which has traditionally been used for post-silicon verification testing, and Cadence, which is known for pre-silicon design and verification. George has proposed the use of NI test hardware and software to do pre-silicon verification in combination with Cadence’s emulation tools, i.e, Palladium. This proposed combination of tools elicited many questions from the audience who were more familiar with the pre-silicon tools than the post-silicon testers. Verification languages were an issue for those who had never used the Mindstorm or other NI graphic tools suits. I’m sure we’ll learn more on this potential partnership between NI and Cadence tool suites.

III. Visionary Talk by Wally Rhines, CEO, Mentor Graphics (prior to the afternoon keynote):

The title described it all; “EDA Grows by Solving New Problems.” Wally’s vision focused on how EDA industry will grow even with the constraints on its relatively flat revenue. As he noted back in the 2004 DAC keynote, the largest growth with EDA tools is associated with the adoption of new methodologies, e.g., ESL, DFM, and FPGAs. Further, tools that support new methodologies have been the main drives of growth in the PCB and semiconductor worlds.

“EDA need to tap into new budgets … for emulation, embedded software … and in new markets,” explained Rhines. “The automotive industry is at the same stage of development as was the chip design industry in the 1970s. Their development process will have to be automated and with new tools.”

Another growth market will be hardware cyber security.

Changing EDA-IP Relationships

June 1st, 2014

Who is really your customer? Competitor? Well-known EDA analyst Gary Smith forecasts the future.

Gary Smith began his annual pre-DAC overview by reminding his audience that in the world of system design (see Figure 1), the OEM was not necessarily a “manufacturer”. In today’s dynamic semiconductor world, the OEM can range from a company buying the platform design, manufacturing the system-on-chip (SoC) at a foundry, wrapping plastic around it and taking it to market (e.g., low end cell phones), to a vertically integrated company that outsources manufacturing (e.g., high-end Apple cell phones).

“With such a range of possible OEM scenarios, you need to understand who is your customer and who is your competitor,” explained Smith. “And the relationships almost change day by day. The key is to develop an ecosystem as stable as ARM’s in this changing world of relationship.”

Figure 1: System design consists of a large continuum, as Smith reminded his EDA audience with his slide from 1996.

System Design (note the capitals) refers to the larger design effort that includes many domains, i.e., hardware, software, electronic, mechanical and more. For the chip design community, system design requires new skills, new marketing and a new organization to participate in the system-level markets that include industrial, consumer, telecom, EDA/Computing, automotive and Mil-Aero. Gary mentioned that, of the big three EDA companies, only Mentor Graphics was actively participating in these markets – for now.

To successfully perform system design across these major markets, serious players must have an expert or multiple experts for each vertical or subset of that vertical. “The expert – most likely a geeky engineer and not a marketing person, drives product definition, but more importantly market access,” said Smith. Not surprisingly, these experts must come from the industry you are addressing.

What role does intellectual property play in this world of system design? “IP” is the key to productivity, therefore low cost design? Or is “IP” a meaningless buzzword used to impress Wall Street?

It’s both, explained Smith. Back in 2011, his analysis showed that “IP” lowered the cost of design by 44% in 2011! But IP is also a hot topic on Wall Street since it seems synonymous with patents. According to Smith, it all started with an EDA marketing person referred to low-level functions as IP. Then other EDA marketing people notice that Wall Street took notice when you mentioned IP and the rest is history.

That’s why one must understand the different kinds of IP. Smith categories ten types of “IP” in his famous wall chart. Each IP type is meant for a different market and has different value and sources:

  • Physical “IP” (2,400 to 74,999 gates)
  • Library “IP”  (“IP” bundles with tools)
  • DesignWare “IP”
  • Large “IP” (75,000 to 999,999 gates) – These designs include hardware, software, and verification IP -  SW, HW and verification IP. It all goes together. (see next bullet)
  • Verification “IP”- Very Large “IP” – Software “IP” (1 million +)

Designing with IP requires a platform. Smith provided a detailed description of the basic platform types, including functional (compute, NoC, etc); Foundation (Snapdragon, i.MX, etc.); and Application (Audio. GPS, etc.) (Editor’s Note: Reference 2012 Presentation: SoC Costs Cut by Multi-Platform Design )

Application Platforms have a short life,” noted Smith. “They are usually integrated into the Foundation Platforms within a few generations. Foundation Platforms are developed by today’s System Providers. Whereas Functional Platforms need a solid ecosystem to survive.”

Moving on to the design process, Smith proclaimed that we now ESL flow at which emulation is the heart. He cautioned that a problem still existed between the system architect and the ESL design group (see Figure 2). “Once the architect hands the design to the ESL group, then they lose control. There are standards for behavioral SystemC. This means that, while the hardware and software guys can use emulators pass things between one another, they can not pass those results back up to the architect.”

Figure 2: ESL flow is real but still has a few challenges.

Some argue that emulation is too expense. But Smith suggests that the real question should be; How does it impact the design cost?  Then short answer is that, in the long run, the impact is small as emulators are being used for many activities beside design (see Figure 3), e.g., bug finder, verification, etc. As companies find multiple uses for emulation, there long term costs will go down. As a consequency, the budget for future emulators will come from a decrease in respins. “If you can save $30 million form one respin, you have the budget to invest $5 million for emulation,” explained  Smith.

Figure 3: Percent HW and SW costs impacted by emulation.

Finally, Smith presented his obligatory 2014 forecast showing a healthy industry getting close to the $10 Billion mark after 2018 (see Figure 4).


Figure 4: The Q2 2014 forecast.


Passion Project for Engineers

May 16th, 2014

Engineers are a creative bunch but what are their passions outside of work? You might be surprised.

Sonia Harrison, Senior PR Manager at Mentor Graphics, recently pinged me about a contest that will culminate at the upcoming Design Automation Conference (DAC). It’s called the “Passion Project” and its goal is to celebrate engineering design creativity.  Engineers are encouraged to show what they love to do outside of work. “We know they are very creative in the workplace, but can bet they are the same during their spare time,” notes Harrison.

Mentor is asking these creative technologists to share their passion with other engineers and those attending DAC. They can do this by submitting a photo and brief description (150 characters) of their hobby. The contest ends on June 3 at 11:59 PST, and the winner, who will be chosen at random, will be awarded a $300 prize on Wednesday of DAC, June 4 at 3:30 pm at the Mentor booth #1733.

Even though I’m also an engineer, I was glad to learn that media editors were also encouraged to participate. Accordingly, I’ll submit my “passion” post in the near future. – JB

Insights from the Sci-Fi Community on Wearables

April 28th, 2014

By John Blyler, Chief Content Officer

Several recent interviews with technical experts about trends in wearable technology made me wonder how sci-fi writers might envision the future.

Just for fun, I asked the Sci-Fi community for their thoughts on the future of wearable technology. The responses ranged from the far-out to the retro and from the quirky to the deeply insightful. The only problem was that I couldn’t resist adding to their comments. Perhaps you’ll find it equally difficult to withhold your own opinions?  – JB

Walter Knight, “America’s Galactic Foreign Legion” series: The most obvious wearable technology I’ve explored in my “America’s Galactic Foreign Legion” science fiction series is the helmet camera, a reality now.  Soldiers, police officers, security guards, etc wear the cameras at work.  Soon, everyone will be wearing these cameras on errands and vacations.  We’ve already seen many news reports showing biker helmet cameras and dash camera.

Privacy concerns are now focused on those the cameras encounter and government intrusion.  But I’m more concerned with the privacy of the wearer of the camera.  What if an employer insists all employees wear the cameras?  Will your union go along with that?  What about bathroom breaks?  Cheating at work?  Picking your nose and flatulence?  Political correctness?  It all gets recorded. Fortunately, there is a low-tech solution if this scenario becomes reality.  Duct tape over the camera lens.  Ha!  Another use for duct tape!

Response from JB: Don’t forget your sentient ATM! That’s sort-of wearable from the perspective of the robot.

Jonathan Howard, Author of the Johannes Cabal, Russalka Chronicles, & Goon Squad series: I can’t honestly say it’s (wearable technology) anything I’ve ever given much thought to, although whoever invents heat-sensitive cloth that moderates its insulating qualities depending on the temperature of the wearer will do very well.

Response from JB: Here’s a bizarre example of a thermal clothing app. It might spark a new product line, e.g.,   liver damage for drinkers, heart trouble for overweight, “I’m lying” for – well, you get it.

The following inputs were provided by the members of the LinkedIn Science Fiction group:

Tracy Shew, Software Development Engineer at Microsoft: Portable lie detectors for the criminally insane. You cannot remove these, like the ankle location detectors we have now for parolees. They measure skin galvanic response, blood pressure, etc., and sound an audible alarm when you attempt to lie. (A plot device in my short, “The Pinocchio Device,” but you are welcomed to it.)

Tom Huber, Retired: The most significant is the personal “net” that changes the visual appearance of the wearer. This technology is far beyond any technology we have today, but it is still something that shows up in SF from time to time. The same device can be used to alter the voice of the wearer.  Another device is the portable / wearable universal translator. It simply provided a translation of a spoken language into the language of the wearer. In addition, it could be used to provide the wearer’s spoken language back into the foreign tongue.

Response from JB: Babel-fish?

Mirjam Maclean, Independent Writer at N Titi Publishing: Magnetic footwear so that wearers could easily scale vertical walls or jump like George Jetson.  And earphones that can echolocate to accurately identifying the location and size of nearby objects.

Jeroen de Wij, Application Manager at Eperium Business Solutions: We will conceivably soon en masse be wearing Google Glasses (and the Apple/Samsung/Motorola/etc alternatives) furthering the always-online world. It won’t be a big leap towards mics worn on a scarf (or even sub dermal) to allow sub-vocalized commands to be sent to devices without being overheard. Earrings/studs/clips to act as small loudspeakers. Some kind of wearable medical technology is imminent, many that has gather press of late appear to be hoaxes but a good (e.g. wrist-) wearable blood pressure and -sugar monitor would seem to be on the near horizon.  — Jeroen de Wij, Application Manager at Eperium Business Solutions

Terry Jackman, Writer, Editor, Reviewer, Speaker, Tutor, Orbit Coordinator at British Science Fiction Association: Camo-suits that ‘hide’ us by mimicking the background, and of course those gloves that operate virtual reality that the flim-makers love. Future wearables might also include clear, flexible breathing masks and faceplates. But not all future wearables might be wearable. For example, I had one instance of far-future government offices reverting to paper messages because nothing else was more secure any longer – the note could be so much more easily kept from sight and/or destroyed than anything hitech – Terry Jackman, Writer, Editor, Reviewer, Speaker, Tutor, Orbit Coordinator at British Science Fiction Association

Suzanna Stinnett, Developmental Editing: In my work-in-progress, set 75 yrs in the future, a herd of 19 year olds are applying for a space program. A calamity between now and then has slowed the advancement of tech in most sectors, but wearable tech was in place before the “Confluence.” The kids are using wearable tech exclusively, meaning they dislike any physical embedding of tech — they’re over it. The soft wristband is ubiquitous, among other ages as well. They also wear bracelets, necklaces and earrings delivering audio and holographic formats. Phones, projected screens, music and data can all be delivered in soft, wearable form. Some wear an adhesive arm patch. The tech is highly interactive, intrusively so. It is activated mainly by a finger swipe, but some kids use a puff of breath to activate. Many of them also have holographic desktop devices, meaning the visual is projected and interacted with holographically.

Steve Hann, Owner at BB&H: In an unpublished satire from 15 years ago, I included tee-shirts that featured tiny LCD bulbs and a belt worn typewriter much like today’s cell phones. People were able to type out messages, and the core idea included built in censorship. If I knew then what I know now…!

I’m not sure you would call it wearable, but I see further advances in the technology that exists now for a micro-chip within the body which has your personal medical record on it. Should you get in an accident anywhere in the world, your complete medical record will be available. Although this technology exists today (for animals), it is extremely expensive and probably not covered by the average insurance company. Further, the average person may feel it as an invasion of privacy and their body. – Cherune Clewley, author, poet and musican

Response from JB: Perhaps a variation on this theme would be DNA or a chromosomal string coded with the person’s medical information. On the other hand, ARM does have a “Well Cow” bolus wireless stomach monitor.   :)

Richard Levine, Software, Education, Science Fiction Writer: Animated tattoos – They’d probably be banned in the NBA, but I would think they’d be pretty popular among celebrities and people wanting to make a statement. I even included one in my time travel short story, “The Time of Your Life” (published Raygun Revival Magazine 2007, issue #15).

Geoff Swift, Materials Scientist/Freelance Writer: Clothing that can purify sweat and urine and store clean water for drinking in survival situations (minimal, sure, but you’re just losing the water anyway).  Piezoelectric chargers in one’s shoes so that every step helps recharge other devices. Filter masks that detect and sound an alarm when various hazardous substances (asbestos, toxic mold, viruses, etc) are present. Should be especially useful for miners, construction/demolition workers, firefighters, and others.  Contact (or implantable) lenses that allow wearer to see infrared for night vision operations (e.g., military).

Allynn Riggs, Owner and lead writer at TimberDark Publications: In my scifi/fantasy series, I have an implanted “bio-teacher” which supplies full language translation (written & verbal), encyclopedia, etc., for times when travelers are on a different planet. The “bio-teacher” is able to learn and adjust its translations the longer the person wearing the device is in contact with the new language – i.e. hearing it being spoken by natives.

Response from JB: Speech recognition, aside from translation, always requires some hefty processing power. But if the implant could connect to the brain and thus benefit from the carbon-based processing, that might significantly lessen the processing needs for the implant.

Ariel Winterbreucke, Independent Publishing Professional: I fear anything I might add would already be in the works or terribly obsolete. The technology is now racing the imagination to the goal line. My idea of the Apple Slice®, which would present your virtual office in 3D through regular Rx eyeglasses and enable you to mime your way through work sitting in a waiting room chair already feels like “oh, yeah, you just spun off GoogleGlass®”. After I told a friend about the earpiece phone in “Minority Report”, he was talking about how his company was just working on that. I’m already into telepathy via telephony, a la the Cerebral Communicators from “The President’s Analyst”. And yet I feel I’ve fallen behind. My defense against changing tech has been to go retro, so maybe this will apply to future tech as well. I can imagine the 1940s being cool again. PCs will hide in pocket watches and it will be cool to use a manual typewriter again, regardless of what it’s really hooked up to. And I’d wear my Apple Slice® with the round Harry Potter lenses riding downtown on the A train, but I’d still keep a pen and regular paper around because I am, after all, an artist. – Ariel Winterbreucke, Independent Publishing Professional

Jennifer Condron-Gold, writer and freelancers: What about a device, cell phone that has the ability to act as an emergency defibrillator for someone in need. Super capacitor?

Response from JB: That could be a real life saver, but the power storage requirement would make it a ticking time-bomb. Maybe it could draw power wirelessly from the surroundings, like a Telsa coil? “Tesla’s Lost Lab Recalls Promise Of Wireless Power

Thadd Evans, Science Fiction writer. Epublished by Devine Destines and Extasy Books: In one of my ebooks, someone places a tiny cell phone like device underneath a detective’s skin. As a result, he can see text and numbers on his field of vision, somewhat like a Terminator. -

Response from JB: Imec, the nanotechnology center in Belgium, has created working prototypes of Google Glass-like wearable contact lens.

Ken Hart, Retired and Writing: For all the technological wonder and usefulness, has anyone considered the dangers inherent with such devices. Liberty and privacy would be lost through tracking transceivers addable to such devices. It’s already happened evidenced by the Wiki-Leaks debacle, and the cell phones you carry. Current and implantable aspects of such devices begs an analogy of becoming Star Trek Borgs.

Response from JB: Perhaps the greater danger is that the tracking organizations (governments) will acquire bad, unverified data from such devices. Just talk to anyone who has mistakenly be placed on the TSA’s naughty list.

Jonathan McGoran, Author at Tor/Forge: Most common ideas of wearable tech are so close on the horizon, they’re just about here. Google is already talking about implants within the next decade. There are also interfaces that are not implanted, but still essentially “thought controlled,” which is a type of wearable tech. Another type of wearable tech, though, is nano-tech, which could change color and texture, or insulating, waterproofing or other capabilities. Add that to the intelligent computer implants, and you have garments that the wearer can drastically alter, while wearing, at the thinking of a thought. -

Response from JB: A very simplistic commercial version of thought control is the “Necomimi” brain-wave cat ears from NeuralSky

Elton Charles Wright, Aerospace Assembly Mechanic: A bracelet that a homeless person could opt into wearing that would get them a bus ride to the nearest place of shelter. A counter idea is an app for a homeless person to locate a place to sleep, but this idea made a lot of assumptions about what a homeless person could afford in technology. Another application might be a hiking poncho that is a solar power supply. You could spread it, use it for a tarp, wear it over the pack to collect power for the gadgets you are carrying, cell/ham/satellite/GPS communicator, a power supply for electric heat/cooking device, and a compatible power tent made of the same power fabric.

Xpedition Awaits for PCB Designers

March 21st, 2014

Mentor Graphics announces improvements to and the re-branding of its well-known Expedition line of printed circuit board (PCB) design and manufacturing tools.

By John Blyler, Chief Content Officer

Earlier this week, Mentor Graphics announced the launch of a new PCB design platform called Xpedition xPCB. The release marks the first phase in an ongoing update of the company’s board-level design and manufacturing tool suites.

The company is integrating its former Expedition PCB suite of tools under the new name. “The first release of the re-branded Xpedition platform aims to greatly improve board-level design productivity,” explained David Wiens, Product Marketing Manager at Mentor.

Today’s board designers face challenges from increasing design complexity and workforce dynamics to the handling of larger systems. Like chips, board designs are growing in complexity with high speed (e.g., 28Gbit) signals, shrinking board sizes with more layers and increasing board densities.

Greater design complexity means that today’s PCB designer efforts are shifting from drafters to board and systems engineers. Unfortunately, there are fewer layout designers in part due to the decline in engineering graduation rates. Adding to these workforce challenges is the move from stand alone PCB projects to more complete systems that include electrical, mechanical and software sub-systems.

Many of these challenges can be met with improvements to design productivity, such as streamlining the design process. Additionally, systematic component placement and planning should be available throughout the development process. The quality and speed of automated routing also should be improved. Finally, PCB development should support both 2D and 3D design, as well as integrate both electronic and mechanical systems.

Xpedition xPCB claims to address all of these challenges. For example, to help streamline the design activity, the platform provides a more consistent and logical user interface, personalized layout toolbars, faster learning curves features and more.

With increasing circuit complexity comes intricate topologies that require more in-depth planning, not to mention the careful placement of thousands of board components. xPCB provides planning and placement features for all of these parts throughout the entire design process, from schematic capture to layout.

Once the design is complete, the board must be routed. The routing environment of xPCB addresses design scenarios including digital and analog subsystem, high-speed signaling plus flex and rigid-flex board implementations.

Routing is tricky. “While automatic routing engines can help, they often add too many vias,” said Charles Pfeil, Engineering Director atMentor. “They also tend to meander. Results from auto routers can take longer than the designers doing it themselves.”

Mentor’s claims that its new routing environment makes it easier for users to get good results with several specific features: sketch router, dynamic router, differential signals, and curved router. The sketch router matches the quality of manual routing but allows the user to manage the location of traces with options for routing styles. It also enables the selection of via patterns. A surprising result is that an optimized, efficient routed selection is also pleasing to the eye, much like a work of art.

Conversely, differential pair routing may not look as good to the casual observer but it is critical for today’s high-speed signals. The challenge with differential pair routing is to maintain symmetrical pad entry as well as trace length and phase matching. “Phase match tuning is all about noise management,” noted Pfeil. “Signals and hence traces that are kept in phase with less impedance mismatch are less susceptible to EMI noise.”

To appreciate the benefits of automating the task of differential pair routing – e.g., quickly moving along rule areas and via pads – check out this video.

Another routing feature of the xPCB tool is the way it handles curved routing, which are needed for BGAs or connectors with staggered pins. The traces for such pins can not be at the usual 45 degrees but instead must be arcs. With high speed signals – around 20GHz, the arcs result in less noise from signal reflections than the more angular 45 degree traces.

The final feature to help increase PCB productivity is in the use of 3D design. Why use 3D techniques in PCB design? Perhaps the biggest benefit is that 3D approaches reduce the errors and resulting iterations between PCB and MCAD designs. A tighter collaboration between the electronic and mechanical board domains is essential in today’s need for full system development.

The other driver in 3D designs is that many applications require a flexible PCB in addition the more traditionally rigid boards.

Xpedition xPCB claims to support true 3D layout instead of just a 2D design interface. The tool boasts a true parametric 3D mechanical kernel, which supports one environment for both 2D and 3D development. The 3D layout designer provides the same features as the 2D version including a generous library of models; component planning, placement and manipulation; constraints and design rule checks; a spatial measurement capabilities. Naturally, the 3D tool has additional features such as board flipping.

In summary, the Xpedition layout platform boasts an automated router that provides hand-routed quality in a shorter design time. Addition, the tool supports component placement and planning, 3D design and validation for minimal MCAD respins, and a better user experience via a more intuitive interface.


This is the first of many announcements under the new Xpedition brand that should make the development and manufacturing of PCBs considerably easier for designers.

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