JB’s Circuit

How do the readers of Chip Design - mostly engineers if one believes the polls - prefer to receive editorial content? Print or Online? This question continues to vex both publishers and advertisers/sponsors alike.

While wrestling with the serious issue of supporting both print and online media, it’s easy for an editor to lose sight of the basics - or so it may seem to the readers. That’s why I thought the follow email exchange between myself and one reader (Jonah) might be instructive and even entertaining. — John

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John. To learn about our industry I mostly use search engines and occasionally hit the front page of eetimes.com.

The ONLY reason that I still subscribe to print editions of magazines is so that I can read different perspectives on our industry from trains, planes, and bed (i.e. places without internet access). When you publish incomplete articles in the print edition of Chip Design Magazine terminated with a web address, I am unlikely to actually go to that web address and I am likely to become frustrated with your publication.

Please only publish complete articles in your print edition or I will demote your print editions to junk status in my paper inbox. Cynically, I doubt that this threat bothers you because as long as you know my address you can charge advertisers based on a higher circulation tally.

~Jonah

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Hi Jonah. You’ve touched on a thorny issue, one for which I am in total agreement as a reader. Why would anyone run an incomplete article in print? One of the values of print - as you note - is to read complete articles when you are beyond the tenuous reach of a wireless connection.

Still, as an editor, the temptations are great. Here are some of the reasons:
1) Attempt to increase the viewership of your website. Yes, this is a poor reason, but “eyeballs” are measurable on the website whereas they are harder to count in print.
2) Shortening articles mean that you can run more pieces, albeit incomplete, in print. With many of my competitions going out of business or serious scaling back their coverage (and removing their print pubs), I’ve been bombarded with contributed pieces - too many to run.
3) Sometimes the demands of production - balancing editorial with advertising pages - requires that articles be shortened. It’s easy for an editor to shorten a piece by merely putting the overrun text online. It takes more work to actually edit a piece and make judicious cuts throughout the article, as we used to do in the old days.

Having said all that, I do agree that running incomplete articles further degrades the value of print. The seeming demise of print is a depressing topic among editors, since most of us dearly love the textual experience of print. But if we want to stay in business, we can not afford to be sentimental.

Nevertheless, I will do my best to run only complete articles in print, even if it requires more work on the part of myself and my staff. That is the right thing to do.

As to your “cynical” comment, let me say this: As a writer, I don’t want to lose readers. You might call it an ego thing, but the reason that I left engineering to become a writer was because I had something to say about the complexities of technology. So I take seriously all legitimate criticisms from my audience.

Didn’t mean to be quite so lengthy in my response, but you hit a nerve. :)   Cheers. — John

BTW: I’d like to run your post and my response on my blog. Believe the readers will find it very interesting. I’ll list your post as “anon,” unless you instruct me otherwise. — John

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John,

Thanks for considering my comments and writing such a thorough reply. You are welcome to publish my comments anonymously or with my name. Please only publish if it will not take page space away from a technical article.

I understand the dilemma of increasing cost and shrinking revenue for publications. It’s a shame and I just wish that I knew a solution.

~Jonah

This post is a follow on to my earlier question: “Do Readers Care Who Pays the Editor?” I was curious to see if our readers (engineers and technical professionals) really care who sponsors the content that they read. The comments to this post have been great and contain responses from both corporate communication experts and the traditional technology press editors.

Predictably, the one critical participant missing from this discussion is the reader, i.e., the engineer and technical professional. In the absence of this critical input, I will venture to speak for them - at least, for a significant portion of this very diverse group. [I believe (hope) that my 20+ years experience as an engineer/program manager qualifies me for this role.]

Here’s how most engineers/managers solve problems in today’s world of high-tech systems: [Caveat: Regardless of the source, content must be well written, technically accurate and relevant to the audience.]

1) Real World - They talk to colleagues at work and at other companies and universities.

2) Online - They perform a keyword search on Google and post questions on very niche forums.
– Google searches will typically lead them to one of two places: corporate websites and trade journal-professional organizational websites.

a) Corporate website content can be extremely useful, but always has the bias of a closed solution space, i.e. content will always reinforce a hardware and/or software product solution that is the specialty of that company.

b) Technology press website content can also be extremely useful and typically cover a broader range of topics. Similarly, the biases are broader than corporate sites, since the range of sponsors tends to dilute the content bias. This can be seen by the fact that good sites cover technology that is beyond the scope of their sponsors.

Both types of technology content coverage are needed - corporate (product focused) and technical press (broader technology focused). One without the other is disastrous. Engineers know this and use both sites accordingly.

Disclaimer: I’m taking off my “engineer” hat and putting back on my “editor” hat: Corporations continue to discover the value of a socially friendly and content rich company website - usually heralded with the announcement of a well-recognized former trade journal editor who will “run” the site (or directing the content generation).  But after the euphoria of launching such a site wears off, many companies begin to realize the importance of participating in the broader discussion offered by technology press websites. One measure of that importance is the capability to drive new customers to the corporate website - both for lead generation and for corporate brand recognition.

Corporate and technical press content sites form a symbiotic relationship. Both must exist for the healthy flow of information. If one is missing, the other won’t last for long.

Designing low-power products requires a greatly customized design which, in turn, requires a great deal of in-house engineering talent and less sharing with external suppliers.

More semiconductor companies are realizing that building products (chips-packages-boards) that consume less power is a market differentiator. But designing low power products isn’t easy. It requires a level of customization that - judging from current business trends - is not feasible in today’s outsourcing model.

One example is Apple’s recent strategy shift away from outsourcing to favoring the cultivation of in-house talent. According to a Wall Street Journal article, Apple has been hiring engineers to design -  really, customize - their multicore cell phone chips. By increasing their in-house design expertise rather than outsourcing it overseas, Apple hopes to create exclusive features through highly customized chip and board sets.

Apple’s strategy shift exemplifies the growing importance of customization.  Low power design requires a high degree of customization in order to meet ever shrinking power budgets that are married with ever increasing product feature sets. In this way, low power design is much like analog-RF design. Another similarity between the two is that customization is not confined to merely chip design. Rather, customization must occur across all levels of product design, including all life cycle phases as well as between domains - from chip to package to board to module to subsystem to final product.

In addition to building up in-house expertise, Apple has made other signs that support the goal of customization. Last April’08, Apple acquired PA Semi,  a key element to controlling power design for the iPhone. Another sign is Apple’s recent hire of the ADMs graphic division CTO, Raja Koduri. All of these trends mean that Apple will be capable of customizing the power, graphics and other key chips in a way that few competitors can match.

These moves toward increased customization capabilities have been mirrored by others in the industry. For example, Intel is pushing hard with its Atom low power embedded processor and recent ventures into the graphics world. ARM, certainly the low power leader in the cellular market, now offer a low power embedded processor for the growing nettop market. Even nVidia, a traditional graphic chip company, is considering building low power products around the x86 architecture.

Customization is a cyclical process (see Makimoto’s Wave). For low-power, it’s not enough to design low power chips. Companies must design low-power process across a number of domains. While not all EDA or semiconductor vendors realize this trend, many do [Chip Designers Scramble For Low-Power Solutions]

Companies that do not will be left “running out of power.”

Sustainable electronic design - often collected under the general title of green electronics - has forced a focused on low power and life-cycle development in a way that has not been experienced since the days of the space race….

Hi all. Sorry for the dry spell in my blogging. Sometime life intercedes and sidetracks our well-heeled routines.

Today I’d like to consider the question of recently displaced editors selling their brand w/o full disclosure. I know how the editorial community feels about such actions, but do readers really care?

Here the problem: What’s an industry-recognized and -respected editor to do once he/she is laid-off by a major publisher? There seems to be one of three career choices:
> Become a freelancer
> Become an editor for a corporation, i.e., EiC for a corporate magazine and/or online site.
> Become an editor for a corporation but give the appearance of still being an independent journalist.

It’s the later case that concerns me. Aside from ethical questions and eventual damage to the editor’s brand, do the readers really care? Can anyone cite examples of the effects on less than full disclosure to the readers (not the editorial community)? Appreciate your thoughts.

Learning about low power design takes a lot of energy. Over the last two months, I’ve interviewed chip companies, IP vendors, EDA suppliers, power organizations, standard bodies and even software development firms.

Each of these groups have a different perspective on the low power problem. Their solutions attest to the range and variety of these perceptions. Yet they also share a common understanding about the changing landscape for electronic products, namely, that power efficiency is now a critical part of the power budget. Let me explain.

In the past, architects would divide up available power – say, battery capacity for a given usage rate – and then allocate a portion of that total power (minus a small reserve) to each block in the chip or board design.

However, today’s power budgets come with an additional caveat: each block is expected to provide a power efficiency improvement as a way to reduce previous power levels. This mandate for efficiency is needed to offset the diverging rise in feature sets with a lack of improvement in battery technology. (See “Chip Designers Scramble For Low Power Solutions,” in the April 15^th Low Power Design e-letter.)

This insistence on power efficiency has forced chip block designers to accelerate their collaboration with both board-level designers and software developers (device drivers, RTOS, OS and applications).

In the past, Time-to-Market (TTM) considerations have been the big driver for system-level awareness. TTM goals have been the main reason for collaboration between hardware chip-package-board and software design teams. But this has changed. While TTM is still important, power efficiency has eclipsed it as the more critical design driver.

What does an obscure announcement about beam epitaxy have to do with system-level design?

Plenty, if you’re designing optical network systems (ONS). Such systems continue to find applications in the macro world of computer network and the micro world of Micro-Electro-Mechanical (MEM) chips. The later requires an understanding of microphotonics, which deals with the direction of light on a microscopic scale.

From a material science standpoint, the really tricky part of micro-optics is in the growth of the appropriate epitaxial layers onto silicon wafers. Epitaxy refers to the method of depositing a monocrystalline film (or epitaxial layer) onto a monocrystalline substrate. The key phrase is “depositing a monocrystalline film,” which requires that similar crystalline structures must be grown (or enticed to grow) onto the surface of the silicon wafer. Epitaxy is used in silicon-based manufacturing processes for BJTs and modern CMOS devices, but also GaAs compounds.

Why am I rambling on about epitaxial layers? Aside from the fact that it’s interesting, measuring the purity of such layers was once part of my job. It’s easy to grow oxides on a silicon substrate – just leave the wafer exposed to air for a few hours. But theses are not the expitaxial layers that you want, especially for microphotonic applications. Growing ferroelectric expitaxial layers is needed for such applications, which, for a number of reasons, is a very difficult task.

Now you can understand why I was interested with the recent announcement from the Center for Nanoscale Materials (CNM) at Argonne National Laboratory.

“Complex Oxide Molecular Beam Epitaxy — This technology allows pure complex oxides films to be grown epitaxially; of special interest are films that are ferroelectric, ferromagnetic, or superconducting. Alternating layers can be deposited to allow the observation of novel properties at the boundary or interface.”

From the obscure world of epitaxy to the common world of optical networks, a good system-level designer must know it all. (Eat your heart out, James Burke.)

There are three critical parameters to which all hardware engineers must pay heed – power, performance and area. The equivalent parameters for software engineers are power (via hardware)-performance and size (memory). While these three elemental factors are dependent upon one another, perhaps the most critical is power. Without power, electronics serve no function aside from esthetics.

Power covers a broad range of topics, from creation and conversion-amplification to delivery. In the chip, package and board world, power design is a nontrivial exercise – just look at the proliferation of tools, formats and methodologies.

Power designs represent real pain-points for hardware and software engineers alike. The last several decades have seen an increasing concern for the shrinking power budgets in chip designs. Today’s consumer movements toward green technology and ever increasing mobility means that low power has become the number one design issue for system architectures through RTL and beyond - to the pack and board level areas, as well.

The challenge of low power, coupled with the increase urgency for such designs, makes the decision to offer a low-power community portal a simple one. The breadth of industries represented by our sponsors - from EDA and IP to even hardware - is a further indication of the importance of this market.

As always, Ed, myself and all our editors look forward to hearing from our readers. Let us know what pain-points you are feeling and what topic areas you’d like to see. Cheers!

Although there were slightly more architectural explorations and trade-off analysis studies performed in January’09 than in the previous month, the overall trend in such investigations continues to decline (see chart). The moving average – which serves as a predictor for trends 3-months out – also declined, but at a sharper rate. This decline is worrisome, but must be balanced with the seasonal trends for this time of year. In past cycles, the first 5 months of any given year have shown similar declines in chip investigations at the architectural level.

This data suggests that chip architects and designers are following seasonal patterns, albeit at a declining rate of new chip projects. Next time, I’ll examine our database of users for trends in which process nodes are dominant.

Over the past year and a half, Synopsys has been acquiring companies and parts of companies in the ASIC prototyping space. Early last year it was Synplicity, while this year it was the ChipIT portion of German-based ProDesign. What is the common thread in these acquisitions? All use FPGA-based hardware and software to prototype complex ASIC designs.

Earlier this week, Synopsys announced its expanded Confirma rapid prototyping platform. Confirma was one of the tool suites acquired from Synplicity. Below is a chart - refreshingly clean and readable - that summaries the acquired tool suits and how they (hopefully) integrate into a whole system:

Integration is the key. I’m particularly interested those areas of functional overlap, such as between original Confirma suite of tools and more recently acquired ChipIT tool. Both tools provide ASIC prototyping capabilities. I discussed some of the issues in a past blog:Hardware Prototyping Market Changes Form

Synopsys’ acquisition of ChipIT would seem to strengthen its position in the system-level development market. Yet many questions remain. First and foremost is how Synopsys will integrate it most recent acquisitions of Synplicity and ProDesign’s ChipIT. For example, which of the two hardware platforms - Synplicity’s Hardi or ProDesign’s ChipIT - will it support, merge or remove? A similar question might be asked on the software side - Synplicity’s Confirma or ProDesign’s ChipIT?

One other question: How will this hardware prototyping platform eventually work with Synpopsys software (virtual) prototyping tool - from the Virtio acquisition?