http://www.chipdesignmag.com/bailey ESL Design and Verification Thu, 15 Sep 2011 14:09:27 +0000 http://backend.userland.com/rss092 en In my last blog, I talked about model-based design and Ken Karnofsky commented on it. Ken is the senior strategist for signal processing algorithms at MathWorks. He said that I got it somewhat wrong and so I was eager to find out more from him. He basically told me that ... http://www.chipdesignmag.com/bailey/2011/09/15/refreshingly-different-mathworks/ A couple of weeks ago I saw a press release go by. The title was “Faraday Accelerates the Development of SoCs with Model-Based Design”. They claimed that this helped them speed up simulation by more than 200X and reduce gate count by more than 50%. Not bad I thought. But ... http://www.chipdesignmag.com/bailey/2011/09/01/grappling-with-model-based-design/ For several decades, the pace of technology development has continued to accelerate. Technologies that used to take years to see significant adoption now seem to happen overnight and the number of things that get integrated together keeps rising. But it seems equally important that everything we buy becomes obsolete as ... http://www.chipdesignmag.com/bailey/2011/08/17/am-i-getting-old/ I am often amazed that any chips actually work. We all know that verification by simulation is based on a sampling of possible stimulus and we also know that the number of samples we provide is a tiny, tiny fraction of all of the possible stimulus patterns. Even so, verification ... http://www.chipdesignmag.com/bailey/2011/08/04/amazing-but-true/ Ah, the joys of summer vacations and scheduling around them. I was disappointed that Synopsys was to have a press release while I was on vacation – especially when it was on one of my favorite topics – virtual prototypes. To make matters worse, by the time I got back, ... http://www.chipdesignmag.com/bailey/2011/07/21/to-the-virtual-prototype-and-beyond/ There have recently been several articles published that relate to System Level Virtual Prototypes (SLVP) and the use of software to verify them. For example Synopsys’ Achim Nohl and Frank Schirrmeister penned an article titled Software Driven Verification. In it they say “…more and more designers not only use embedded ... http://www.chipdesignmag.com/bailey/2011/07/07/are-you-positive-about-that-verification-approach/ Let me take a stroll down memory lane. The year is 2009 and it is DAC. On a panel put together by Lucio Lanza, a long time EDA and semiconductor investor, they came to the conclusion that chips are costing $50-100M and that is too much. They said the return ... http://www.chipdesignmag.com/bailey/2011/06/15/don%e2%80%99t-listen-to-the-experts-they-have-it-backwards/ Last week I was helping a friend put on an art exhibition in Columbia, CA, a preserved gold mining town from the mid 1800s. I wrote about that in my personal blog. In the few hours that I had free, I went to nearby Jamestown – a historic short line ... http://www.chipdesignmag.com/bailey/2011/06/02/design-evolution-locks-you-into-local-minima/ So, we are nearing the end of the biggest stimulus spending package that this country has seen, and I wonder what we really have to show for it. A few filled pot holes, perhaps a junction or two that flows a little easier than it once did. But in a ... http://www.chipdesignmag.com/bailey/2011/05/19/stimulus-done-right/ It seems as if all of the major EDA vendors have now come to the realization that RTL simulation is just not a total solution anymore. Gone are the days when it was the one tool that would be used for all aspects verification from implementation through integration to system-level ... http://www.chipdesignmag.com/bailey/2011/05/05/the-simulator-is-no-longer-enough/