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	<title>Verification Vertigo</title>
	<link>http://www.chipdesignmag.com/bailey</link>
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	<lastBuildDate>Wed, 17 Sep 2008 13:46:09 +0000</lastBuildDate>
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		<title>Bye bye Cadence</title>
		<description> 
Last week it was CDNlive down in San Jose, the Cadence captive conference where they showcase all of their new and exciting technologies and share their roadmaps with their customers. I was there for two days and presented a session on Wednesday afternoon about the application of mutation analysis ...</description>
		<link>http://www.chipdesignmag.com/bailey/2008/09/16/bye-bye-cadence/</link>
			</item>
	<item>
		<title>Congrats to NuSym</title>
		<description> 

NuSym, one of the companies vying for the emerging intelligent testbench space, has just managed to raise $8M in venture funding to help bring their technology to market. This is on top of the $8M they received back in 2005 when they were exploring the technology. As I wrote ...</description>
		<link>http://www.chipdesignmag.com/bailey/2008/09/11/congrats-to-nusym/</link>
			</item>
	<item>
		<title>Shame on you big EDA companies!</title>
		<description> 

An important piece of standards work is being undertaken within Accellera. It is the creation of a standard API related to coverage data and is being conducted under the UCIS committee. 18 months ago, a request for donations was made. All of the major EDA companies declined to accept ...</description>
		<link>http://www.chipdesignmag.com/bailey/2008/08/28/shame-on-you-big-eda-companies/</link>
			</item>
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		<title>Flexibility is a key talent</title>
		<description>
 

I have just returned from England, where I helped my parents celebrate their 60th wedding anniversary – an event where even the Queen sends them a congratulatory card.

Just a little under a year ago, I helped them move from the house they had lived in for 50 years, the ...</description>
		<link>http://www.chipdesignmag.com/bailey/2008/08/19/flexibility-is-a-key-talent/</link>
			</item>
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		<title>Slow, Cumbersome and Incomplete</title>
		<description>With the recent announcement of nVidia purchasing rights to use the Transmeta power optimizing portfolio of patents I though it was time to talk about the problems of low power and verification. A recent book by Synopsys and ARM was disappointing in that it really did not address this issue ...</description>
		<link>http://www.chipdesignmag.com/bailey/2008/08/11/13/</link>
			</item>
	<item>
		<title>When is the time right?</title>
		<description> Most of the time, standards get created after the EDA industry knows what it wants. This is either because a defacto standard has already emerged, or the industry has enough knowledge to be confident in the solution it is creating. In other cases, such as the recent developments in ...</description>
		<link>http://www.chipdesignmag.com/bailey/2008/07/31/when-is-the-time-right/</link>
			</item>
	<item>
		<title>Positive and Negative Verification</title>
		<description> In a previous blog, I talked about the differences between verification and validation. What can confuse those definitions even more is when we start looking at verification in a hierarchical manner. This hierarchical process also brings in another fundamental distinction, namely that of positive and negative verification. In the ...</description>
		<link>http://www.chipdesignmag.com/bailey/2008/07/21/positive-and-negative-verification/</link>
			</item>
	<item>
		<title>The Verification Wave</title>
		<description> 
Many things in our industry go in cycles. Perhaps the most famous of these is Makimoto’s wave which identifies the cyclic oscillation between standardized and customized semiconductors with a 10-year cycle.




An email exchange with one of my clients and an article in Mentor’s latest issue of Verification News reminded ...</description>
		<link>http://www.chipdesignmag.com/bailey/2008/07/11/the-verification-wave/</link>
			</item>
	<item>
		<title>EDA Standards</title>
		<description> For the EDA industry, standards are traditionally defined by the EDA companies. While end users often attend the first few meetings of a new standards venture, few of them have the time or inclination to spend the many hours it takes to work through the technical details or the ...</description>
		<link>http://www.chipdesignmag.com/bailey/2008/06/24/eda-standards/</link>
			</item>
	<item>
		<title>My theme for DAC was&#8230;</title>
		<description>Perhaps the most common question at DAC is “What did you find that was new and interesting?” I often wonder if this is because they had not found anything themselves and need some ideas, or that there is so much information flying around, that they have problems sorting out the ...</description>
		<link>http://www.chipdesignmag.com/bailey/2008/06/16/my-theme-for-dac-was/</link>
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