VMM-LP is the result of years of experience of low power industry leaders and documents best practices and a blueprint to enable comprehensive, repeatable and productive verification of low power designs. It’s in response to the growing importance and difficulty of comprehensively verifying a low power design before it is committed to silicon. VMM-LP is also an answer to “slow, cumbersome and incomplete” verification of low power designs.

VMM-LP includes a book that describes the common causes of failures in low power designs, a “how-to” manual on setting up a verification environment for low power including power-aware assertions, coverage, and test plans, and a methodology for a scalable and reusable infrastructure for verification of low power designs.

Importantly, VMM-LP also includes free access to source code under an Apache 2.0 license for a System-Verilog base class library that is aware of the simulation semantics of power shutdown and retention and helps create the reusable verification environment. There is tremendous interest and excellent progress in the VMM-LP effort. Both the book and the base classes are scheduled for release in fall 2008. People interested in being notified immediately on the availability of the book and class library can register at http://www.vmmcentral.org.

So, we look forward to your feedback then!

You also mention MVSIM with VCS as a Synopsys solution for verification of low power designs but don’t recognize that MVSIM has been in active use for more than 3 years and became part of the Synopsys product portfolio last year through Synopsys’ acquisition of ArchPro. MVSIM and MVRC were specifically designed to address the growing problem of low power verification - MVSIM from a simulation perspective and MVRC from a static perspective. They have helped designers successfully weed out power management bugs prior to silicon and prevented re-spins. MVSIM also implements a lot of the verification methodology that is now being documented in the VMM-LP book, and Cypress and Renesas have been public in discussing their successes. With the VMM-LP effort, Synopsys and other low power leaders are making available in public domain the methodology already implemented and proved in MVSIM.

Thanks for highlighting the importance of verification to low power design!
-phil

Now, you mentioned detecting illegal behavior. This is somewhat more difficult and qualifying the testbench can can tell you about behavior that may be missing in the design. So if code should exist to recover from a situation, then you may have a problem. Having said that, both the design and the testbench would have to be missing this functionality, or functional qualification would have detected it. If you want more information on this, I suggest that you contact Certess directly.

Last year I took a course in SystemVerilog and it appeared to me there was no convenient way to confirm that the SystemVerilog code was indeed catching all the illegal behavior I was expecting it to do. The instructor confirmed there was no tool support he knew of in industry to help verify the testbench itself. Neither did the class address technique(s) for accomplishing this.

Please comment on this. Do you know of any commercial tool support for this? With the advent of SystemVerilog rules, what are the the/some recommended techniques for verifying the robustness of the rules?

However, I’ve found that the engineers’s love of a standard methodology quickly slips away when they are actually presented with one. This is because the proposed methodology is “too big” or “too small” or “too OOPy” or “not OOPy enough” or “too confusing” or “too simplistic” or “too open” or “too closed” or “too new” or “too old” and always “Not Invented Here.”

I applaud your comment that the user community should let their voices be heard. I wonder, though, if they will all say something that can result in a standard.