Verification Vertigo

Most of the time, standards get created after the EDA industry knows what it wants. This is either because a defacto standard has already emerged, or the industry has enough knowledge to be confident in the solution it is creating. In other cases, such as the recent developments in the Unified Coverage Interoperability group [...]

In a previous blog, I talked about the differences between verification and validation. What can confuse those definitions even more is when we start looking at verification in a hierarchical manner. This hierarchical process also brings in another fundamental distinction, namely that of positive and negative verification. In the book ESL Design and Verification [...]

Many things in our industry go in cycles. Perhaps the most famous of these is Makimoto’s wave which identifies the cyclic oscillation between standardized and customized semiconductors with a 10-year cycle.

An email exchange with one of my clients and an article in Mentor’s latest issue of Verification News reminded me of another wave in [...]

No blog on verification would be complete without a discussion about what verification actual is – and this is a subject that is near and dear to my heart. In discussions with EDA vendors and users, it is clear that they sometimes forget the fundamentals – and so I always include a small section about [...]

Welcome to this my first blog for Chip Design magazine. My background has always been functional verification ever since I started my first job – designing flight control computers for commercial aircraft. It appalled me that we did not use simulators, instead relying only on physical prototypes made out of wire wrap cards. During my [...]