The ESL Edge

Archive for the 'background' Category

04
Aug

Amazing but True

I am often amazed that any chips actually work. We all know that verification by simulation is based on a sampling of possible stimulus and we also know that the number of samples we provide is a tiny, tiny fraction of all of the possible stimulus patterns. Even so, verification is taking up a larger [...]

07
Jul

Are you Positive about that Verification Approach?

Is it enough to verify a system using the actual software? Brian Bailey says no. We need a balanced approach between proving functionality works and eliminating bugs.

02
Jun

Design Evolution locks you into Local Minima

Last week I was helping a friend put on an art exhibition in Columbia, CA, a preserved gold mining town from the mid 1800s. I wrote about that in my personal blog. In the few hours that I had free, I went to nearby Jamestown – a historic short line railway that has been turned [...]

07
Apr

A Plethora of Hierarchies

It wasn’t so very long ago that the high-level synthesis vendors were arguing over the correct language to use.  Should it be C, C++, SystemC or some other language, such as M? Their arguments ranged over several issues including which was more abstract, which was faster to write, simulate and debug, which one contained more [...]

07
Apr

I am back and welcome to “The ESL Edge”

It has been about 18 months since I was actively blogging on this site and it feels good to be back. In the last incarnation, I blogged on the Verification Vertigo feed. This time, I am changing the scope a little to blog about the emerging area of ESL. I intend to talk about languages, [...]

30
Jul

Accuracy does not imply accuracy!!

It is always great to receive compliments after giving a presentation. While many people may say good job, or nice presentation, it is even better when you get the kinds of comments I received after a presentation I gave at the DAC Workshop for virtual platforms in San Francisco on Wednesday morning. To put [...]

31
Jul

When is the time right?

Most of the time, standards get created after the EDA industry knows what it wants. This is either because a defacto standard has already emerged, or the industry has enough knowledge to be confident in the solution it is creating. In other cases, such as the recent developments in the Unified Coverage Interoperability group [...]

21
Jul

Positive and Negative Verification

In a previous blog, I talked about the differences between verification and validation. What can confuse those definitions even more is when we start looking at verification in a hierarchical manner. This hierarchical process also brings in another fundamental distinction, namely that of positive and negative verification. In the book ESL Design and Verification [...]

11
Jul

The Verification Wave

Many things in our industry go in cycles. Perhaps the most famous of these is Makimoto’s wave which identifies the cyclic oscillation between standardized and customized semiconductors with a 10-year cycle.

An email exchange with one of my clients and an article in Mentor’s latest issue of Verification News reminded me of another wave in [...]

15
May

Verification defined

No blog on verification would be complete without a discussion about what verification actual is – and this is a subject that is near and dear to my heart. In discussions with EDA vendors and users, it is clear that they sometimes forget the fundamentals – and so I always include a small section about [...]

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