Verification Vertigo

Limor Fix writes:

I am very proud of DAC’s program this year. As usual, the program is so rich that it is impossible to cover all of it in only a few words. Thus, I have chosen to tell you about one of the many “diamonds” in the DAC technical program.

Session 28, “Jumping the High-Level Verification Hurdle,” is a must-attend session for every design and verification engineer to be held Wednesday, July 29, from 2-4pm.

Chaired by Somdipta Basu Roy of Texas Instruments, exciting new technologies and methodologies will be described, including how untimed behavioral models can be used to model and verify a high-level model of an ESL design. Attendees will learn how SystemVerilog is used for modeling and simulation-based verification of the high-level model and moreover, how the same model is used as a formal specification for the RTL implementations.  Additionally, presenters will highlight how advances in sequential equivalence verification allow for formal verification among models with different abstraction levels, that is, equivalence verification between the high-level model and the RTL.

Overall, important progress and great achievements are reported in the challenging area of system-level design and verification and I’m looking forward to hearing all of the details.

This isn’t the only session dedicated to the all-important category of verification and test. In fact, there are 18 sessions devoted to this topic, from one User Track session and four tutorials and special sessions to four technical sessions on verification and test.

An additional eight sessions are found on the DAC website and will be held at the IC Design Central Partner Pavilion or as part of the Exhibitor Forum or are additional meetings hosted by exhibitors.

For those of you seeking a more practical look at today’s verification challenges and solutions, check out the one final verification session, a pavilion panel called, “Seeking the Holy Grail of Verification Coverage Closure.” Chaired by Brian Bailey, author of this blog –– Verification Vertigo –– and noted verification consultant, it promises a look at the range of technologies available to meet this goal. Speakers include Jim Sullivan of Qualcomm, Jon Michelson from Cisco, David Bural of Texas Instruments and JL Gray of Verilab and author of the Cool Verification blog. Brian’s panel will coincide with the technical session on high-level verification –– Wednesday starting at 2 p.m.

DAC will host more than 200 vendors in this year’s exhibit hall, from industry leaders Cadence, Magma, Mentor and Synopsys to Atrentra, CoWare, EVE, Jasper, GateRocket, Nusym and Real Intent. The January 15 issue of DACeZine’s directory of verification tools has a more complete listing of verification vendors. For details, visit: www.dac.com/newsletter/shownewsletter.aspx?newsid=69

I encourage you to attend DAC and participate in the all-important industry discussions affecting all of us. See you in San Francisco!

Limor Fix works at Intel Labs in Pittsburg and is the Past Chair for the 46th DAC.

Thanks Limor, and thanks for the plug for my panel. It is too bad that verification events have to overlap each other, as well as the all day Virtual Platform Workshop on Wednesday that I will be participating in. However, it is good to see that at long last, verification is beginning to command the presence that it deserves at DAC.