The ESL Edge

When OSCI came out with TLM 1.0, the industry almost laughed at it. It did nothing to help alleviate the problems of interconnecting IP described at abstractions above the RTL level. Then last year, TLM 2.0 was released. The industry response was “too little, too late” and most IP vendors and EDA companies said that it did not offer enough for them to adopt it. They pointed out that the proprietary interfaces they had developed were faster and better and it was not worth the time to retrofit all of their existing IP. But then it seems, reality set in and they started to realize that interoperability is more important than a little bit of performance.

Earlier this week, I learned of another convert. This time it was the folks at Imperas, who released OVP last year as a free and open way to model processors and processor based platforms for software development. They have now done an integration that they believe offers the best of both worlds: OVP for modeling processors and SystemC/TLM 2.0 for connecting models together. While they can still model peripherals as well, most of them are likely to be available as third party IP modeled in SystemC.

Their integration also includes support for DMI which allows the processor models to directly access memory, rather than having to access it through the slower TLM interface. This is useful to accelerate execution when it is not necessary to see all of the transactions passing over the bus model.

They are currently seeing about a 3% degradation over their own proprietary interfaces but believe that this can be reduced further. They are demonstrating systems running at between 200 and 500 MIPS on a 2GHz laptop computer

They also informed me that most of their efforts are now going back to being spent on the original goal of the company, namely tools that will help with the development, debug and verification of multi-processor systems.