Verification Vertigo

I am excited today to be able to talk about a new product that I had to keep quiet about for some time. First of all some disclosure. I am on the Technical Advisory Board of Jasper Design Automation and it was associated with that role that I first learned about some developments that they were working on. Richard Goering wrote an article about it on SCDSource which will provide you with a lot more of the background. I also had to sort of keep quiet about it at the Austin DVClub a few months ago. During that presentation, I hinted about it, but could not provide specifics.

What makes this so exciting is that it is the first time that engineers developing RTL code have had the ability to ask questions about the code they are creating without having to create a testbench, or waiting until the block is finished. A tool that will allow them to question design decisions as they are made and find out some of the consequences of those decisions. ActiveDesign is the product name and behavioral indexing is the technical term that they have coined for what it does. It basically allows you to build knowledge about the design as you progress, often in the form of scenarios or use cases, that are preserved as properties. This knowledge can then be used to test ideas or assess the impact of making an architectural change. It will tell you if functionality has been preserved or what impact it has on timing, or if behaviors are no longer possible. While not a replacement for existing verification, this can ensure that the RTL that is produced is of higher quality that before. In my DVClub presentation “Is it time to declare a verification war?”, which I will be repeating in San Jose in March, I left the last line to Sun Tzu. He said “To subdue the enemy without fighting is the supreme excellence”. This product gets us one step closer to that verification dream.