Aug
Slow, Cumbersome and Incomplete
With the recent announcement of nVidia purchasing rights to use the Transmeta power optimizing portfolio of patents I though it was time to talk about the problems of low power and verification. A recent book by Synopsys and ARM was disappointing in that it really did not address this issue at all, just saying that the addition of low power technology makes verification more difficult. Thanks guys - big help! [Keating, Flynn, Aitken, Gibbons and Shi. Low Power Methodology Manual for System-on-Chip Design. Springer 2007]. In a paper by Freescale and Cadence they discuss the problems of RTL verification and conclude:
“While it is possible to use ad-hoc methods to verify these design elements, the methods are often far from ideal and can be slow, cumbersome and incomplete. “
More recently, Synopsys announced a new product that brings voltage awareness to the verification problem. They say:
“MVSIM co-simulates with VCS. VCS performs functional simulation of the logic elements and MVSIM simulates the power-management functions within a design. The result is a completely verified power-managed design.�
They also have a multi-voltage extension to their formal rule checker.
Power management verification consists of a number of different areas, such as correct level shifters and isolation logic, that all design instances are connected to the correct supply, that the correct registers are preserving state during power down, and many other aspects. One of the things necessary is a way to specify power management functions so that tools can automate the process of including the right data in the simulations. I am not talking about just the gate level, but the higher levels of abstraction so that proper architectural tradeoffs can be considered and verified long before the actual implementation. The HDLs really do not include any constructs to describe power.
Synopsys also announced some low power assertion technology recently. While this does not verify the power management intent, it does check that an implementation implement what is necessary. For example, if a region is meant to be powered down, then none of the clocks in that region should be active
At this years DVCon – two sessions existed on the subject of low-power verification, a testament to how important this topic is becoming. With its awareness growing, I hope it is not long before someone comes up with a way to describe power-intent and then I would have more hope that this issue will receive some real solutions. Until then it will be – in the words of Cadence – slow, cumbersome and incomplete.
Brian - thanks for pointing out the importance and challenges of verification posed by power management. Also, thanks for pointing out the “Low Power Methodology Manual” (LPMM), which is a perfect book for getting a strong practical understanding of designing for low power, especially architecture and implementation. You’re correct that the LPMM didn’t include a lot of verification depth, and that’s why ARM, Renesas, and Synopsys have been collaborating to produce the first verification methodology for low power designs (”VMM-LP”). The VMM-LP also includes as co-author, David Flynn from ARM, a co-author of the LPMM.
VMM-LP is the result of years of experience of low power industry leaders and documents best practices and a blueprint to enable comprehensive, repeatable and productive verification of low power designs. It’s in response to the growing importance and difficulty of comprehensively verifying a low power design before it is committed to silicon. VMM-LP is also an answer to “slow, cumbersome and incomplete” verification of low power designs.
VMM-LP includes a book that describes the common causes of failures in low power designs, a “how-to” manual on setting up a verification environment for low power including power-aware assertions, coverage, and test plans, and a methodology for a scalable and reusable infrastructure for verification of low power designs.
Importantly, VMM-LP also includes free access to source code under an Apache 2.0 license for a System-Verilog base class library that is aware of the simulation semantics of power shutdown and retention and helps create the reusable verification environment. There is tremendous interest and excellent progress in the VMM-LP effort. Both the book and the base classes are scheduled for release in fall 2008. People interested in being notified immediately on the availability of the book and class library can register at http://www.vmmcentral.org.
So, we look forward to your feedback then!
You also mention MVSIM with VCS as a Synopsys solution for verification of low power designs but don’t recognize that MVSIM has been in active use for more than 3 years and became part of the Synopsys product portfolio last year through Synopsys’ acquisition of ArchPro. MVSIM and MVRC were specifically designed to address the growing problem of low power verification - MVSIM from a simulation perspective and MVRC from a static perspective. They have helped designers successfully weed out power management bugs prior to silicon and prevented re-spins. MVSIM also implements a lot of the verification methodology that is now being documented in the VMM-LP book, and Cypress and Renesas have been public in discussing their successes. With the VMM-LP effort, Synopsys and other low power leaders are making available in public domain the methodology already implemented and proved in MVSIM.
Thanks for highlighting the importance of verification to low power design!
August 14th, 2008 at 5:27 pm-phil