Jul
When is the time right?
Most of the time, standards get created after the EDA industry knows what it wants. This is either because a defacto standard has already emerged, or the industry has enough knowledge to be confident in the solution it is creating. In other cases, such as the recent developments in the Unified Coverage Interoperability group within Accellera, it happens because users demand it. But there are times when a new technology is emerging and interested parties need to be brought together, with the view to formulating something that will serve the needs of many people, and create a foundation for the accelerated adoption of a technology. What I am referring to is the creation of a standard fault model for HDL models.
Let me digress for a while. It is important to understand the difference between an error model and a fault model. Think back to the days of manufacturing test, before SCAN and other such techniques. We needed a set of vectors that would ensure that all faults in the device would be activated and propagated to an output where a comparison could be made. If a particular chip or board produced results different from the reference, then the part was deemed bad. A typical problem in a chip or board would either be an open circuit or a short circuit between two points. However, a fault model called the stuck at model was adopted. It said that if every wire was tied first the ground rail and then the supply rail, and the vectors applied, that if we could detect all of those faults, then their was also a very good chance that we would be able to detect actual errors in the system. Thus the fault model was not the same as the error model, but a relationship had been established in terms of the quality of results.
OK, so back to the HDL world. There is a growing need to have a fault model for this higher level of abstraction. In a Design and Test article [1] this month, the authors called for a fault model to help them analyze transient faults in systems as the geometries get so small, that stray particles are likely to cause errors, or as parts age. In an interview with Hana Chockler conducted by Richard Goering[2], Chockler called for the creation of a fault model to help in the creation of closure metrics for formal methods. The third part concerned, is a company called Certess[3] that has been using mutation based analysis to find weaknesses in verification environments, and some of their customers are asking for the fault model to be standardized.
So it seems to me that there are enough people working in the same area and direction to warrant an industry discussion on this subject. I wish there were a way and a forum that such industry discussion could happen without it inevitably leading to a standard, but rather an industry position paper or statement. In some regards I always thought that VSIA served in this role, and while it did produce standards, it was the industry discussion that it fostered that was perhaps even more important. It allowed an industry to come together and talk about their common problems and potential solutions. That is what we need here.
[1] – Austin, Bertacco, Mahlke and Cao. Reliable systems on Unreliable Fabrics. Design and Test. July/August 2008
[2] – Coverage metrics gain ground in formal verification. SCDsource July 31st 2008 http://www.scdsource.com/experts.php?id=282
[3] – Certess corporate website http://certess.com
