Jul
The Verification Wave
Many things in our industry go in cycles. Perhaps the most famous of these is Makimoto’s wave which identifies the cyclic oscillation between standardized and customized semiconductors with a 10-year cycle.
An email exchange with one of my clients and an article in Mentor’s latest issue of Verification News reminded me of another wave in our industry. The subject matter is verification languages. In the early 80’s the waveform language was a separate and distinct language – at that time purely for defining stimulus sets by assigning values at specific times. More sophisticated languages emerged over the next few years that brought in behavioral programming constructs. Then along came Verilog and basically the design and verification languages merged into a single language. About 10 years later, with the introduction of Vera and Specman e, a new generation of separate languages emerged. Once these had reached their climax, they too were incorporated into the design language – SystemVerilog (Well sort of. They are still separate languages within a common syntactic shell).
We are now seeing the third generation of separate verification languages – those related to the new class of intelligent testbenches. From these graph based languages (that does not imply graphics, as one industry pundit believes), a condensed set of functional vectors can be generated that cover all possible behaviors. These languages are in essence the first form of executable specification that the industry has seen, and I can’t help thinking that these may someday also become the way in which we design systems – thus seeing the languages come together again.
As always your views and comments are welcomed.
Keeping you covered
Brian Bailey
