May
DAC for Verification
Here is my condensation about everything I know of going on at DAC this year that is related to verification. It includes the actual program, co-located events and the companies that will be exhibiting. If you know of anything missing from this list, please post it here as a comment. If you would like to arrange a meeting with me at DAC, please do so quickly as my calender is filling up fast.
DAC Program
MONDAY - June 09, 2008
HANDS-ON TUTORIAL: Elevating Confidence in Design IP Through Mutation-based Analysis Technology - Certess, Inc. / STMicroelectronics / Brian Bailey Consulting
9:00 AM - 12:00 PM / Room: 213D
I will be presenting as part of this Hands-On session.
What you Should Know about The Open Verification Methodology (OVM)
10:50 AM - 11:30 AM Exhibitor Forum – Mentor Graphics
It may be vendor specific, but could provide some valuable information. Also see the Pavilion panel on Thursday.
WORKSHOP: Beyond Syntax and Semantics: Industry Experiences with OVL/SVA/PSL
1:00 PM - 5:15 PM / Room: 207D
TUESDAY - June 10, 2008
Accellera Technical Committee Update and Technical Excellence Award
11:00 AM - 1:00 PM / Room: Exhibit Hall D, Booth2849
Sure to include some information on their newly formed Verification IP committee
ADDITIONAL MEETING: Verification Luncheon
12:00 PM - 2:00 PM / Room: Marriott-Ballroom E
Lunch is on Synopsys, but they are not providing much guidance on what they will be talking about.
Session 9: Formal Verification Technology
2:00 PM - 4:00 PM / Room: 208AB
This is about advancements in formal verification and attempts to make it more scalable
Session 15: Experiences and Advances in Formal and Dynamic Verification
4:30 PM - 6:00 PM / Room: 208AB
A mixed bag of technical papers
WEDNESDAY - June 11, 2008
Session 30: PANEL: Verifying Really Complex Systems: On Earth and Beyond
2:00 PM - 4:00 PM / Room: 210CD
This could be an interesting insight into how people traditionally outside of the EDA world deal with verification. Speakers include ones from Boeing and NASA.
THURSDAY - June 12, 2008
PAVILION PANEL: Your Functional Verification Roadmap: OVM, VMM, or Roll Your Own?
11:00 AM - 11:45 AM / Room: Booth #364
This is a must be at event – why? – because yours truly is the moderator for this match up between the three competing verification methodologies
Session 44: SPECIAL SESSION: Formal Verification: Dude or Dud? Experiences from the Trenches
2:00 PM - 4:00 PM / Room: 207ABC
It seems that this is a staple of most conferences these days. Asking the question – will formal ever really get in gear? I think we all know the answer already. For certain designs it already has, for others there is little or no hope. Fit the right solution to the problem
Session 51: Advances in Verification of Abstract (pre-RTL) Models
4:30 PM - 6:00 PM / Room: 208AB
These papers discuss verification of SystemC and C++ models in a mix of formal and dynamic verification methods.
Co-located Events
6th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE)
June 5-7, 2008
7th Symposium on Electronic System-level Design with SystemC
June 8-9, 2008
Additional Meetings
MONDAY - June 09, 2008
Writing Efficient TLM 2.0 Models with GreenSocs
9:00am to 10:30am – Hilton Hotel
Doulos Solutions Workshop 1 with Cadence - “Migrating to OVM for Multi-language Verification-How to Enable VIP Inter-operability”
12:15 PM - 2:00 PM / Room: 201A
TUESDAY - June 10, 2008
ADDITIONAL MEETING: Verification Luncheon
12:00 PM - 2:00 PM / Room: Marriott-Ballroom E
WEDNESDAY - June 11, 2008
ADDITIONAL MEETING: Variation Robustness for Analog/Mixed-Signal, Custom Digital and Memory Design
9:00 AM - 10:00 AM / Room: Anaheim Hilton - El Capitan AB
12:00 PM - 2:00 PM / Room: Ballroom E
Doulos Solutions Workshop 2 with Mentor Graphics - “Getting Real with OVM, a True Open Source Verification Standard”
12:15 PM - 2:00 PM / Room: 201A
Companies
New this year
Axilica Ltd.
Booth Number(s): 1373
High level modeling using UML. According to their write-up:
With Axilica’s tool-set, designs can be simulated or immediately realised in hardware at any stage in the refinement process, whether it’s the rapid prototyping and partitioning of a high-level design, or the realisation of a complete hardware/software system-on-chip. The technology integrates with existing electronic design flows and also supports the generation of transaction-level models for high-speed simulation.
Paradigm Works, Inc.
Booth Number(s): 2318
While Paradigm works is hardly a new company, this is their first time at DAC. They provide design and verification services. During the course of their engagements, they have developed their own tools to help provide even more verification productivity.
WinterLogic Inc.
Booth Number(s): 2767
And I thought that fault simulation was a thing of the past! This company is providing a Verilog fault simulator that covers all levels of abstraction from transaction to transistor. Supports stuck-at faults, transition and bridging faults.
Been there before, but still new
Breker Verification Systems
Booth Number(s): 2741
One of the new intelligent testbench companies based on the use of graphs for test creation.
Calypto Design Systems
Booth Number(s): 1354
Sequential analysis leader enabling higher levels of equivalence checking.
Certess
Booth Number(s): 324
Mutation analysis and functional qualification provide an objective way to measure coverage and testbench quality.
CoFluent Design
Booth Number(s): 654
An ESL modeling and simulation company.
Doulos
Booth Number(s): 2300
Training on just about everything related to verification.
Imperas
Booth Number(s): 467
High performance virtual prototypes for software verification
Instigate
Booth Number(s): 770
Provides HW/SW co-verification products
Jasper Design Automation
Booth Number(s): 2346
A provider of formal verification and verification planning tools. Specializes in deep formal proving.
Jeda technologies
Booth Number(s): 2231
Provides extensions to SystemC such as assertions and coverage.
Legend Design Automation
Booth Number(s): 1733
Spice simulator.
Liga Systems
Booth Number(s): 300
Accelerators for 3rd party commercial RTL simulators.
Mirabilis Design
Booth Number(s): 778
ESL analysis and simulation, including SystemC entry and execution.
NuSym Technologies
Booth Number(s): 379
While they were at DAC last year, this is the first year that they have had a story to tell, having just come out of stealth mode. A new approach on the intelligent testbench story.
OneSpin Solutions
Booth Number(s): 625
RTL formal verification using SystemVerilog assertions
ProDesign Automation
Booth Number(s): 344
FPGA based simulation accelerator
RealIntent
Booth Number(s): 2540
Assertion based RTL formal verification
SynFora
Booth Number(s): 329
ESL verification at untimed C level.
VeriEZ Solutions
Booth Number(s): 1936
Linters for SystemVerilog and OpenVera plus testbench translators.
Verific Design Automation
Booth Number(s): 655
Language parsers for EDA tools
Veritools
Booth Number(s): 1334
RTL and below verification and analysis tools
Xoomsys
Booth Number(s): 310
Distributed analog, mixed-signal simulation
Been around for a long time
Agilent Technologies
Booth Number(s): 1601
If your into high frequency, then their EESof products are not going to be new to you.
Aldec
Booth Number(s): 1600
Verilog and VHDL simulation along with a variety of other verification tools.
Ansoft Corp
Booth Number(s): 1301
Analog simulation, specializing in the simulation of multi-gigabit systems for optimization of channel performance.
Atrenta
Booth Number(s): 2327
Formal analysis of designs looking for trouble spots
Averant
Booth Number(s): 834
A formal verification company supporting PSL, HPL, OVA, and OVL
Avery Design Systems
Booth Number(s): 355
Semi formal analysis for bug hunting and analysis and provider of VIP
Axiom Design Automation
Booth Number(s): 1471
Multi-CPU simulation and verification tools and services
Berkeley Design Automation
Booth Number(s): 2641
Fast spice simulator provider.
Carbon Design Systems
Booth Number(s): 2467
They create high performance models from RTL implementation filling the gap in legacy models for system level virtual prototypes.
CoWare
Booth Number(s): 1625
Platform driven ESL tool provider based on SystemC
Denali
Booth Number(s): 1611
Provider of Verification IP
Dini Group
Booth Number(s): 1528
Provider of FPGA prototyping boards
Dynalith
Booth Number(s): 1431
Provider of behavioral emulation systems
Magma Design Automation
Booth Number(s): 2349
Gate, transistor and spice simulation
The Mathworks
Booth Number(s): 741
ESL entry and simulation, especially dataflow. Links with 3rd party RTL simulation
Mentor Graphics
Booth Number(s): 2301
Full line EDA supplier with verification software all the way from ESL down to physical
Nascentric
Booth Number(s): 1571
Transistor level simulation.
National Instruments
Booth Number(s): 659
An interesting coupling between the ESL and instrumentation world.
Novas
Booth Number(s): 1300
Design comprehension and analysis solutions
SimuCAD design automation
Booth Number(s): 1140
Analog, mixed-signal simulation
Synopsys
Booth Number(s): 1349
Full line verification supplier from the ESL level all the way down to physical. Their recent acquisition of Synplicity also adds prototyping to the mix.
I always like to get emails from people. brian_bailey at acm dot org
